1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 * Korey Sewell
42 */
43
44#include "arch/registers.hh"
45#include "config/the_isa.hh"
46#include "cpu/o3/thread_context.hh"
47#include "cpu/quiesce_event.hh"
48
49#if FULL_SYSTEM
50template <class Impl>
51VirtualPort *
52O3ThreadContext<Impl>::getVirtPort()
53{
54 return thread->getVirtPort();
55}
56
57template <class Impl>
58void
59O3ThreadContext<Impl>::dumpFuncProfile()
60{
61 thread->dumpFuncProfile();
62}
63#endif
64
65template <class Impl>
66void
67O3ThreadContext<Impl>::takeOverFrom(ThreadContext *old_context)
68{
69 // some things should already be set up
70#if FULL_SYSTEM
71 assert(getSystemPtr() == old_context->getSystemPtr());
72#else
73 assert(getProcessPtr() == old_context->getProcessPtr());
74#endif
75
76 // copy over functional state
77 setStatus(old_context->status());
78 copyArchRegs(old_context);
79 setContextId(old_context->contextId());
80 setThreadId(old_context->threadId());
81
82#if !FULL_SYSTEM
83 thread->funcExeInst = old_context->readFuncExeInst();
84#else
85 EndQuiesceEvent *other_quiesce = old_context->getQuiesceEvent();
86 if (other_quiesce) {
87 // Point the quiesce event's TC at this TC so that it wakes up
88 // the proper CPU.
89 other_quiesce->tc = this;
90 }
91 if (thread->quiesceEvent) {
92 thread->quiesceEvent->tc = this;
93 }
94
95 // Transfer kernel stats from one CPU to the other.
96 thread->kernelStats = old_context->getKernelStats();
97// storeCondFailures = 0;
98 cpu->lockFlag = false;
99#endif
100
101 old_context->setStatus(ThreadContext::Halted);
102
103 thread->inSyscall = false;
104 thread->trapPending = false;
105}
106
107template <class Impl>
108void
109O3ThreadContext<Impl>::activate(int delay)
110{
111 DPRINTF(O3CPU, "Calling activate on Thread Context %d\n",
112 threadId());
113
114 if (thread->status() == ThreadContext::Active)
115 return;
116
117#if FULL_SYSTEM
118 thread->lastActivate = curTick();
119#endif
120
121 thread->setStatus(ThreadContext::Active);
122
123 // status() == Suspended
124 cpu->activateContext(thread->threadId(), delay);
125}
126
127template <class Impl>
128void
129O3ThreadContext<Impl>::suspend(int delay)
130{
131 DPRINTF(O3CPU, "Calling suspend on Thread Context %d\n",
132 threadId());
133
134 if (thread->status() == ThreadContext::Suspended)
135 return;
136
137#if FULL_SYSTEM
138 thread->lastActivate = curTick();
139 thread->lastSuspend = curTick();
140#endif
141/*
142#if FULL_SYSTEM
143 // Don't change the status from active if there are pending interrupts
144 if (cpu->checkInterrupts()) {
145 assert(status() == ThreadContext::Active);
146 return;
147 }
148#endif
149*/
150 thread->setStatus(ThreadContext::Suspended);
151 cpu->suspendContext(thread->threadId());
152}
153
154template <class Impl>
155void
156O3ThreadContext<Impl>::halt(int delay)
157{
158 DPRINTF(O3CPU, "Calling halt on Thread Context %d\n",
159 threadId());
160
161 if (thread->status() == ThreadContext::Halted)
162 return;
163
164 thread->setStatus(ThreadContext::Halted);
165 cpu->haltContext(thread->threadId());
166}
167
168template <class Impl>
169void
170O3ThreadContext<Impl>::regStats(const std::string &name)
171{
172#if FULL_SYSTEM
173 thread->kernelStats = new TheISA::Kernel::Statistics(cpu->system);
174 thread->kernelStats->regStats(name + ".kern");
175#endif
176}
177
178template <class Impl>
179void
180O3ThreadContext<Impl>::serialize(std::ostream &os)
181{
182#if FULL_SYSTEM
183 if (thread->kernelStats)
184 thread->kernelStats->serialize(os);
185#endif
186
187}
188
189template <class Impl>
190void
191O3ThreadContext<Impl>::unserialize(Checkpoint *cp, const std::string &section)
192{
193#if FULL_SYSTEM
194 if (thread->kernelStats)
195 thread->kernelStats->unserialize(cp, section);
196#endif
197
198}
199
200#if FULL_SYSTEM
201template <class Impl>
202Tick
203O3ThreadContext<Impl>::readLastActivate()
204{
205 return thread->lastActivate;
206}
207
208template <class Impl>
209Tick
210O3ThreadContext<Impl>::readLastSuspend()
211{
212 return thread->lastSuspend;
213}
214
215template <class Impl>
216void
217O3ThreadContext<Impl>::profileClear()
218{
219 thread->profileClear();
220}
221
222template <class Impl>
223void
224O3ThreadContext<Impl>::profileSample()
225{
226 thread->profileSample();
227}
228#endif
229
230template <class Impl>
231void
232O3ThreadContext<Impl>::copyArchRegs(ThreadContext *tc)
233{
234 // Prevent squashing
235 thread->inSyscall = true;
236 TheISA::copyRegs(tc, this);
237 thread->inSyscall = false;
238
239#if !FULL_SYSTEM
240 this->thread->funcExeInst = tc->readFuncExeInst();
241#endif
242}
243
244template <class Impl>
245void
246O3ThreadContext<Impl>::clearArchRegs()
247{
248 cpu->isa[thread->threadId()].clear();
249}
250
251template <class Impl>
252uint64_t
253O3ThreadContext<Impl>::readIntReg(int reg_idx)
254{
255 reg_idx = cpu->isa[thread->threadId()].flattenIntIndex(reg_idx);
256 return cpu->readArchIntReg(reg_idx, thread->threadId());
257}
258
259template <class Impl>
260TheISA::FloatReg
261O3ThreadContext<Impl>::readFloatReg(int reg_idx)
262{
263 reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
264 return cpu->readArchFloatReg(reg_idx, thread->threadId());
265}
266
267template <class Impl>
268TheISA::FloatRegBits
269O3ThreadContext<Impl>::readFloatRegBits(int reg_idx)
270{
271 reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
272 return cpu->readArchFloatRegInt(reg_idx, thread->threadId());
273}
274
275template <class Impl>
276void
277O3ThreadContext<Impl>::setIntReg(int reg_idx, uint64_t val)
278{
279 reg_idx = cpu->isa[thread->threadId()].flattenIntIndex(reg_idx);
280 cpu->setArchIntReg(reg_idx, val, thread->threadId());
281
282 // Squash if we're not already in a state update mode.
283 if (!thread->trapPending && !thread->inSyscall) {
284 cpu->squashFromTC(thread->threadId());
285 }
286}
287
288template <class Impl>
289void
290O3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val)
291{
292 reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
293 cpu->setArchFloatReg(reg_idx, val, thread->threadId());
294
295 if (!thread->trapPending && !thread->inSyscall) {
296 cpu->squashFromTC(thread->threadId());
297 }
298}
299
300template <class Impl>
301void
302O3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
303{
304 reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
305 cpu->setArchFloatRegInt(reg_idx, val, thread->threadId());
306
307 // Squash if we're not already in a state update mode.
308 if (!thread->trapPending && !thread->inSyscall) {
309 cpu->squashFromTC(thread->threadId());
310 }
311}
312
313template <class Impl>
314void
315O3ThreadContext<Impl>::pcState(const TheISA::PCState &val)
316{
317 cpu->pcState(val, thread->threadId());
318
319 // Squash if we're not already in a state update mode.
320 if (!thread->trapPending && !thread->inSyscall) {
321 cpu->squashFromTC(thread->threadId());
322 }
323}
324
325template <class Impl>
326int
327O3ThreadContext<Impl>::flattenIntIndex(int reg)
328{
329 return cpu->isa[thread->threadId()].flattenIntIndex(reg);
330}
331
332template <class Impl>
333int
334O3ThreadContext<Impl>::flattenFloatIndex(int reg)
335{
336 return cpu->isa[thread->threadId()].flattenFloatIndex(reg);
337}
338
339template <class Impl>
340void
341O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
342{
343 cpu->setMiscRegNoEffect(misc_reg, val, thread->threadId());
344
345 // Squash if we're not already in a state update mode.
346 if (!thread->trapPending && !thread->inSyscall) {
347 cpu->squashFromTC(thread->threadId());
348 }
349}
350
351template <class Impl>
352void
353O3ThreadContext<Impl>::setMiscReg(int misc_reg,
354 const MiscReg &val)
355{
356 cpu->setMiscReg(misc_reg, val, thread->threadId());
357
358 // Squash if we're not already in a state update mode.
359 if (!thread->trapPending && !thread->inSyscall) {
360 cpu->squashFromTC(thread->threadId());
361 }
362}
363