1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 * Korey Sewell
30 */
31
32#include "cpu/o3/thread_context.hh"
33#include "cpu/quiesce_event.hh"
34
35#if FULL_SYSTEM
36template <class Impl>
37VirtualPort *
38O3ThreadContext<Impl>::getVirtPort(ThreadContext *src_tc)
39{
40 if (!src_tc)
41 return thread->getVirtPort();
42
43 VirtualPort *vp;
44 Port *mem_port;
45
46 vp = new VirtualPort("tc-vport", src_tc);
47 mem_port = cpu->system->physmem->getPort("functional");
48 mem_port->setPeer(vp);
49 vp->setPeer(mem_port);
50 return vp;
51}
52
53template <class Impl>
54void
55O3ThreadContext<Impl>::dumpFuncProfile()
56{
57 thread->dumpFuncProfile();
58}
59#endif
60
61template <class Impl>
62void
63O3ThreadContext<Impl>::takeOverFrom(ThreadContext *old_context)
64{
65 // some things should already be set up
66#if FULL_SYSTEM
67 assert(getSystemPtr() == old_context->getSystemPtr());
68#else
69 assert(getProcessPtr() == old_context->getProcessPtr());
70#endif
71
72 // copy over functional state
73 setStatus(old_context->status());
74 copyArchRegs(old_context);
75 setCpuId(old_context->readCpuId());
76
77#if !FULL_SYSTEM
78 thread->funcExeInst = old_context->readFuncExeInst();
79#else
80 EndQuiesceEvent *other_quiesce = old_context->getQuiesceEvent();
81 if (other_quiesce) {
82 // Point the quiesce event's TC at this TC so that it wakes up
83 // the proper CPU.
84 other_quiesce->tc = this;
85 }
86 if (thread->quiesceEvent) {
87 thread->quiesceEvent->tc = this;
88 }
89
90 // Transfer kernel stats from one CPU to the other.
91 thread->kernelStats = old_context->getKernelStats();
92// storeCondFailures = 0;
93 cpu->lockFlag = false;
94#endif
95
96 old_context->setStatus(ThreadContext::Unallocated);
97
98 thread->inSyscall = false;
99 thread->trapPending = false;
100}
101
102#if FULL_SYSTEM
103template <class Impl>
104void
105O3ThreadContext<Impl>::delVirtPort(VirtualPort *vp)
106{
107 delete vp->getPeer();
108 delete vp;
109}
110#endif
111
112template <class Impl>
113void
114O3ThreadContext<Impl>::activate(int delay)
115{
116 DPRINTF(O3CPU, "Calling activate on Thread Context %d\n",
117 getThreadNum());
118
119 if (thread->status() == ThreadContext::Active)
120 return;
121
122#if FULL_SYSTEM
123 thread->lastActivate = curTick;
124#endif
125
126 if (thread->status() == ThreadContext::Unallocated) {
127 cpu->activateWhenReady(thread->readTid());
128 return;
129 }
130
131 thread->setStatus(ThreadContext::Active);
132
133 // status() == Suspended
134 cpu->activateContext(thread->readTid(), delay);
135}
136
137template <class Impl>
138void
139O3ThreadContext<Impl>::suspend()
140{
141 DPRINTF(O3CPU, "Calling suspend on Thread Context %d\n",
142 getThreadNum());
143
144 if (thread->status() == ThreadContext::Suspended)
145 return;
146
147#if FULL_SYSTEM
148 thread->lastActivate = curTick;
149 thread->lastSuspend = curTick;
150#endif
151/*
152#if FULL_SYSTEM
153 // Don't change the status from active if there are pending interrupts
154 if (cpu->check_interrupts()) {
155 assert(status() == ThreadContext::Active);
156 return;
157 }
158#endif
159*/
160 thread->setStatus(ThreadContext::Suspended);
161 cpu->suspendContext(thread->readTid());
162}
163
164template <class Impl>
165void
166O3ThreadContext<Impl>::deallocate(int delay)
167{
168 DPRINTF(O3CPU, "Calling deallocate on Thread Context %d delay %d\n",
169 getThreadNum(), delay);
170
171 if (thread->status() == ThreadContext::Unallocated)
172 return;
173
174 thread->setStatus(ThreadContext::Unallocated);
175 cpu->deallocateContext(thread->readTid(), true, delay);
176}
177
178template <class Impl>
179void
180O3ThreadContext<Impl>::halt()
181{
182 DPRINTF(O3CPU, "Calling halt on Thread Context %d\n",
183 getThreadNum());
184
185 if (thread->status() == ThreadContext::Halted)
186 return;
187
188 thread->setStatus(ThreadContext::Halted);
189 cpu->haltContext(thread->readTid());
190}
191
192template <class Impl>
193void
194O3ThreadContext<Impl>::regStats(const std::string &name)
195{
196#if FULL_SYSTEM
197 thread->kernelStats = new TheISA::Kernel::Statistics(cpu->system);
198 thread->kernelStats->regStats(name + ".kern");
199#endif
200}
201
202template <class Impl>
203void
204O3ThreadContext<Impl>::serialize(std::ostream &os)
205{
206#if FULL_SYSTEM
207 if (thread->kernelStats)
208 thread->kernelStats->serialize(os);
209#endif
210
211}
212
213template <class Impl>
214void
215O3ThreadContext<Impl>::unserialize(Checkpoint *cp, const std::string §ion)
216{
217#if FULL_SYSTEM
218 if (thread->kernelStats)
219 thread->kernelStats->unserialize(cp, section);
220#endif
221
222}
223
224#if FULL_SYSTEM
225template <class Impl>
226Tick
227O3ThreadContext<Impl>::readLastActivate()
228{
229 return thread->lastActivate;
230}
231
232template <class Impl>
233Tick
234O3ThreadContext<Impl>::readLastSuspend()
235{
236 return thread->lastSuspend;
237}
238
239template <class Impl>
240void
241O3ThreadContext<Impl>::profileClear()
242{
243 thread->profileClear();
244}
245
246template <class Impl>
247void
248O3ThreadContext<Impl>::profileSample()
249{
250 thread->profileSample();
251}
252#endif
253
254template <class Impl>
255TheISA::MachInst
256O3ThreadContext<Impl>:: getInst()
257{
258 return thread->getInst();
259}
260
261template <class Impl>
262void
263O3ThreadContext<Impl>::copyArchRegs(ThreadContext *tc)
264{
265 // This function will mess things up unless the ROB is empty and
266 // there are no instructions in the pipeline.
267 unsigned tid = thread->readTid();
268 PhysRegIndex renamed_reg;
269
270 // First loop through the integer registers.
271 for (int i = 0; i < TheISA::NumIntRegs; ++i) {
272 renamed_reg = cpu->renameMap[tid].lookup(i);
273
274 DPRINTF(O3CPU, "Copying over register %i, had data %lli, "
275 "now has data %lli.\n",
276 renamed_reg, cpu->readIntReg(renamed_reg),
277 tc->readIntReg(i));
278
279 cpu->setIntReg(renamed_reg, tc->readIntReg(i));
280 }
281
282 // Then loop through the floating point registers.
283 for (int i = 0; i < TheISA::NumFloatRegs; ++i) {
284 renamed_reg = cpu->renameMap[tid].lookup(i + TheISA::FP_Base_DepTag);
285 cpu->setFloatRegBits(renamed_reg,
286 tc->readFloatRegBits(i));
287 }
288
289 // Copy the misc regs.
290 TheISA::copyMiscRegs(tc, this);
291
292 // Then finally set the PC and the next PC.
293 cpu->setPC(tc->readPC(), tid);
294 cpu->setNextPC(tc->readNextPC(), tid);
295#if !FULL_SYSTEM
296 this->thread->funcExeInst = tc->readFuncExeInst();
297#endif
298}
299
300template <class Impl>
301void
302O3ThreadContext<Impl>::clearArchRegs()
303{}
304
305template <class Impl>
306uint64_t
307O3ThreadContext<Impl>::readIntReg(int reg_idx)
308{
309 return cpu->readArchIntReg(reg_idx, thread->readTid());
310}
311
312template <class Impl>
313TheISA::FloatReg
314O3ThreadContext<Impl>::readFloatReg(int reg_idx, int width)
315{
316 switch(width) {
317 case 32:
318 return cpu->readArchFloatRegSingle(reg_idx, thread->readTid());
319 case 64:
320 return cpu->readArchFloatRegDouble(reg_idx, thread->readTid());
321 default:
322 panic("Unsupported width!");
323 return 0;
324 }
325}
326
327template <class Impl>
328TheISA::FloatReg
329O3ThreadContext<Impl>::readFloatReg(int reg_idx)
330{
331 return cpu->readArchFloatRegSingle(reg_idx, thread->readTid());
332}
333
334template <class Impl>
335TheISA::FloatRegBits
336O3ThreadContext<Impl>::readFloatRegBits(int reg_idx, int width)
337{
338 DPRINTF(Fault, "Reading floatint register through the TC!\n");
339 return cpu->readArchFloatRegInt(reg_idx, thread->readTid());
340}
341
342template <class Impl>
343TheISA::FloatRegBits
344O3ThreadContext<Impl>::readFloatRegBits(int reg_idx)
345{
346 return cpu->readArchFloatRegInt(reg_idx, thread->readTid());
347}
348
349template <class Impl>
350void
351O3ThreadContext<Impl>::setIntReg(int reg_idx, uint64_t val)
352{
353 cpu->setArchIntReg(reg_idx, val, thread->readTid());
354
355 // Squash if we're not already in a state update mode.
356 if (!thread->trapPending && !thread->inSyscall) {
357 cpu->squashFromTC(thread->readTid());
358 }
359}
360
361template <class Impl>
362void
363O3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val, int width)
364{
365 switch(width) {
366 case 32:
367 cpu->setArchFloatRegSingle(reg_idx, val, thread->readTid());
368 break;
369 case 64:
370 cpu->setArchFloatRegDouble(reg_idx, val, thread->readTid());
371 break;
372 }
373
374 // Squash if we're not already in a state update mode.
375 if (!thread->trapPending && !thread->inSyscall) {
376 cpu->squashFromTC(thread->readTid());
377 }
378}
379
380template <class Impl>
381void
382O3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val)
383{
384 cpu->setArchFloatRegSingle(reg_idx, val, thread->readTid());
385
386 if (!thread->trapPending && !thread->inSyscall) {
387 cpu->squashFromTC(thread->readTid());
388 }
389}
390
391template <class Impl>
392void
393O3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val,
394 int width)
395{
396 DPRINTF(Fault, "Setting floatint register through the TC!\n");
397 cpu->setArchFloatRegInt(reg_idx, val, thread->readTid());
398
399 // Squash if we're not already in a state update mode.
400 if (!thread->trapPending && !thread->inSyscall) {
401 cpu->squashFromTC(thread->readTid());
402 }
403}
404
405template <class Impl>
406void
407O3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
408{
409 cpu->setArchFloatRegInt(reg_idx, val, thread->readTid());
410
411 // Squash if we're not already in a state update mode.
412 if (!thread->trapPending && !thread->inSyscall) {
413 cpu->squashFromTC(thread->readTid());
414 }
415}
416
417template <class Impl>
418void
419O3ThreadContext<Impl>::setPC(uint64_t val)
420{
421 cpu->setPC(val, thread->readTid());
422
423 // Squash if we're not already in a state update mode.
424 if (!thread->trapPending && !thread->inSyscall) {
425 cpu->squashFromTC(thread->readTid());
426 }
427}
428
429template <class Impl>
430void
431O3ThreadContext<Impl>::setNextPC(uint64_t val)
432{
433 cpu->setNextPC(val, thread->readTid());
434
435 // Squash if we're not already in a state update mode.
436 if (!thread->trapPending && !thread->inSyscall) {
437 cpu->squashFromTC(thread->readTid());
438 }
439}
440
441template <class Impl>
442void
443O3ThreadContext<Impl>::setMiscReg(int misc_reg, const MiscReg &val)
444{
445 cpu->setMiscReg(misc_reg, val, thread->readTid());
446
447 // Squash if we're not already in a state update mode.
448 if (!thread->trapPending && !thread->inSyscall) {
449 cpu->squashFromTC(thread->readTid());
450 }
451}
452
453template <class Impl>
454void
455O3ThreadContext<Impl>::setMiscRegWithEffect(int misc_reg,
456 const MiscReg &val)
457{
458 cpu->setMiscRegWithEffect(misc_reg, val, thread->readTid());
459
460 // Squash if we're not already in a state update mode.
461 if (!thread->trapPending && !thread->inSyscall) {
462 cpu->squashFromTC(thread->readTid());
463 }
464}
465
466#if !FULL_SYSTEM
467
468template <class Impl>
469TheISA::IntReg
470O3ThreadContext<Impl>::getSyscallArg(int i)
471{
472 return cpu->getSyscallArg(i, thread->readTid());
473}
474
475template <class Impl>
476void
477O3ThreadContext<Impl>::setSyscallArg(int i, IntReg val)
478{
479 cpu->setSyscallArg(i, val, thread->readTid());
480}
481
482template <class Impl>
483void
484O3ThreadContext<Impl>::setSyscallReturn(SyscallReturn return_value)
485{
486 cpu->setSyscallReturn(return_value, thread->readTid());
487}
488
489#endif // FULL_SYSTEM
490
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 * Korey Sewell
30 */
31
32#include "cpu/o3/thread_context.hh"
33#include "cpu/quiesce_event.hh"
34
35#if FULL_SYSTEM
36template <class Impl>
37VirtualPort *
38O3ThreadContext<Impl>::getVirtPort(ThreadContext *src_tc)
39{
40 if (!src_tc)
41 return thread->getVirtPort();
42
43 VirtualPort *vp;
44 Port *mem_port;
45
46 vp = new VirtualPort("tc-vport", src_tc);
47 mem_port = cpu->system->physmem->getPort("functional");
48 mem_port->setPeer(vp);
49 vp->setPeer(mem_port);
50 return vp;
51}
52
53template <class Impl>
54void
55O3ThreadContext<Impl>::dumpFuncProfile()
56{
57 thread->dumpFuncProfile();
58}
59#endif
60
61template <class Impl>
62void
63O3ThreadContext<Impl>::takeOverFrom(ThreadContext *old_context)
64{
65 // some things should already be set up
66#if FULL_SYSTEM
67 assert(getSystemPtr() == old_context->getSystemPtr());
68#else
69 assert(getProcessPtr() == old_context->getProcessPtr());
70#endif
71
72 // copy over functional state
73 setStatus(old_context->status());
74 copyArchRegs(old_context);
75 setCpuId(old_context->readCpuId());
76
77#if !FULL_SYSTEM
78 thread->funcExeInst = old_context->readFuncExeInst();
79#else
80 EndQuiesceEvent *other_quiesce = old_context->getQuiesceEvent();
81 if (other_quiesce) {
82 // Point the quiesce event's TC at this TC so that it wakes up
83 // the proper CPU.
84 other_quiesce->tc = this;
85 }
86 if (thread->quiesceEvent) {
87 thread->quiesceEvent->tc = this;
88 }
89
90 // Transfer kernel stats from one CPU to the other.
91 thread->kernelStats = old_context->getKernelStats();
92// storeCondFailures = 0;
93 cpu->lockFlag = false;
94#endif
95
96 old_context->setStatus(ThreadContext::Unallocated);
97
98 thread->inSyscall = false;
99 thread->trapPending = false;
100}
101
102#if FULL_SYSTEM
103template <class Impl>
104void
105O3ThreadContext<Impl>::delVirtPort(VirtualPort *vp)
106{
107 delete vp->getPeer();
108 delete vp;
109}
110#endif
111
112template <class Impl>
113void
114O3ThreadContext<Impl>::activate(int delay)
115{
116 DPRINTF(O3CPU, "Calling activate on Thread Context %d\n",
117 getThreadNum());
118
119 if (thread->status() == ThreadContext::Active)
120 return;
121
122#if FULL_SYSTEM
123 thread->lastActivate = curTick;
124#endif
125
126 if (thread->status() == ThreadContext::Unallocated) {
127 cpu->activateWhenReady(thread->readTid());
128 return;
129 }
130
131 thread->setStatus(ThreadContext::Active);
132
133 // status() == Suspended
134 cpu->activateContext(thread->readTid(), delay);
135}
136
137template <class Impl>
138void
139O3ThreadContext<Impl>::suspend()
140{
141 DPRINTF(O3CPU, "Calling suspend on Thread Context %d\n",
142 getThreadNum());
143
144 if (thread->status() == ThreadContext::Suspended)
145 return;
146
147#if FULL_SYSTEM
148 thread->lastActivate = curTick;
149 thread->lastSuspend = curTick;
150#endif
151/*
152#if FULL_SYSTEM
153 // Don't change the status from active if there are pending interrupts
154 if (cpu->check_interrupts()) {
155 assert(status() == ThreadContext::Active);
156 return;
157 }
158#endif
159*/
160 thread->setStatus(ThreadContext::Suspended);
161 cpu->suspendContext(thread->readTid());
162}
163
164template <class Impl>
165void
166O3ThreadContext<Impl>::deallocate(int delay)
167{
168 DPRINTF(O3CPU, "Calling deallocate on Thread Context %d delay %d\n",
169 getThreadNum(), delay);
170
171 if (thread->status() == ThreadContext::Unallocated)
172 return;
173
174 thread->setStatus(ThreadContext::Unallocated);
175 cpu->deallocateContext(thread->readTid(), true, delay);
176}
177
178template <class Impl>
179void
180O3ThreadContext<Impl>::halt()
181{
182 DPRINTF(O3CPU, "Calling halt on Thread Context %d\n",
183 getThreadNum());
184
185 if (thread->status() == ThreadContext::Halted)
186 return;
187
188 thread->setStatus(ThreadContext::Halted);
189 cpu->haltContext(thread->readTid());
190}
191
192template <class Impl>
193void
194O3ThreadContext<Impl>::regStats(const std::string &name)
195{
196#if FULL_SYSTEM
197 thread->kernelStats = new TheISA::Kernel::Statistics(cpu->system);
198 thread->kernelStats->regStats(name + ".kern");
199#endif
200}
201
202template <class Impl>
203void
204O3ThreadContext<Impl>::serialize(std::ostream &os)
205{
206#if FULL_SYSTEM
207 if (thread->kernelStats)
208 thread->kernelStats->serialize(os);
209#endif
210
211}
212
213template <class Impl>
214void
215O3ThreadContext<Impl>::unserialize(Checkpoint *cp, const std::string §ion)
216{
217#if FULL_SYSTEM
218 if (thread->kernelStats)
219 thread->kernelStats->unserialize(cp, section);
220#endif
221
222}
223
224#if FULL_SYSTEM
225template <class Impl>
226Tick
227O3ThreadContext<Impl>::readLastActivate()
228{
229 return thread->lastActivate;
230}
231
232template <class Impl>
233Tick
234O3ThreadContext<Impl>::readLastSuspend()
235{
236 return thread->lastSuspend;
237}
238
239template <class Impl>
240void
241O3ThreadContext<Impl>::profileClear()
242{
243 thread->profileClear();
244}
245
246template <class Impl>
247void
248O3ThreadContext<Impl>::profileSample()
249{
250 thread->profileSample();
251}
252#endif
253
254template <class Impl>
255TheISA::MachInst
256O3ThreadContext<Impl>:: getInst()
257{
258 return thread->getInst();
259}
260
261template <class Impl>
262void
263O3ThreadContext<Impl>::copyArchRegs(ThreadContext *tc)
264{
265 // This function will mess things up unless the ROB is empty and
266 // there are no instructions in the pipeline.
267 unsigned tid = thread->readTid();
268 PhysRegIndex renamed_reg;
269
270 // First loop through the integer registers.
271 for (int i = 0; i < TheISA::NumIntRegs; ++i) {
272 renamed_reg = cpu->renameMap[tid].lookup(i);
273
274 DPRINTF(O3CPU, "Copying over register %i, had data %lli, "
275 "now has data %lli.\n",
276 renamed_reg, cpu->readIntReg(renamed_reg),
277 tc->readIntReg(i));
278
279 cpu->setIntReg(renamed_reg, tc->readIntReg(i));
280 }
281
282 // Then loop through the floating point registers.
283 for (int i = 0; i < TheISA::NumFloatRegs; ++i) {
284 renamed_reg = cpu->renameMap[tid].lookup(i + TheISA::FP_Base_DepTag);
285 cpu->setFloatRegBits(renamed_reg,
286 tc->readFloatRegBits(i));
287 }
288
289 // Copy the misc regs.
290 TheISA::copyMiscRegs(tc, this);
291
292 // Then finally set the PC and the next PC.
293 cpu->setPC(tc->readPC(), tid);
294 cpu->setNextPC(tc->readNextPC(), tid);
295#if !FULL_SYSTEM
296 this->thread->funcExeInst = tc->readFuncExeInst();
297#endif
298}
299
300template <class Impl>
301void
302O3ThreadContext<Impl>::clearArchRegs()
303{}
304
305template <class Impl>
306uint64_t
307O3ThreadContext<Impl>::readIntReg(int reg_idx)
308{
309 return cpu->readArchIntReg(reg_idx, thread->readTid());
310}
311
312template <class Impl>
313TheISA::FloatReg
314O3ThreadContext<Impl>::readFloatReg(int reg_idx, int width)
315{
316 switch(width) {
317 case 32:
318 return cpu->readArchFloatRegSingle(reg_idx, thread->readTid());
319 case 64:
320 return cpu->readArchFloatRegDouble(reg_idx, thread->readTid());
321 default:
322 panic("Unsupported width!");
323 return 0;
324 }
325}
326
327template <class Impl>
328TheISA::FloatReg
329O3ThreadContext<Impl>::readFloatReg(int reg_idx)
330{
331 return cpu->readArchFloatRegSingle(reg_idx, thread->readTid());
332}
333
334template <class Impl>
335TheISA::FloatRegBits
336O3ThreadContext<Impl>::readFloatRegBits(int reg_idx, int width)
337{
338 DPRINTF(Fault, "Reading floatint register through the TC!\n");
339 return cpu->readArchFloatRegInt(reg_idx, thread->readTid());
340}
341
342template <class Impl>
343TheISA::FloatRegBits
344O3ThreadContext<Impl>::readFloatRegBits(int reg_idx)
345{
346 return cpu->readArchFloatRegInt(reg_idx, thread->readTid());
347}
348
349template <class Impl>
350void
351O3ThreadContext<Impl>::setIntReg(int reg_idx, uint64_t val)
352{
353 cpu->setArchIntReg(reg_idx, val, thread->readTid());
354
355 // Squash if we're not already in a state update mode.
356 if (!thread->trapPending && !thread->inSyscall) {
357 cpu->squashFromTC(thread->readTid());
358 }
359}
360
361template <class Impl>
362void
363O3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val, int width)
364{
365 switch(width) {
366 case 32:
367 cpu->setArchFloatRegSingle(reg_idx, val, thread->readTid());
368 break;
369 case 64:
370 cpu->setArchFloatRegDouble(reg_idx, val, thread->readTid());
371 break;
372 }
373
374 // Squash if we're not already in a state update mode.
375 if (!thread->trapPending && !thread->inSyscall) {
376 cpu->squashFromTC(thread->readTid());
377 }
378}
379
380template <class Impl>
381void
382O3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val)
383{
384 cpu->setArchFloatRegSingle(reg_idx, val, thread->readTid());
385
386 if (!thread->trapPending && !thread->inSyscall) {
387 cpu->squashFromTC(thread->readTid());
388 }
389}
390
391template <class Impl>
392void
393O3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val,
394 int width)
395{
396 DPRINTF(Fault, "Setting floatint register through the TC!\n");
397 cpu->setArchFloatRegInt(reg_idx, val, thread->readTid());
398
399 // Squash if we're not already in a state update mode.
400 if (!thread->trapPending && !thread->inSyscall) {
401 cpu->squashFromTC(thread->readTid());
402 }
403}
404
405template <class Impl>
406void
407O3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
408{
409 cpu->setArchFloatRegInt(reg_idx, val, thread->readTid());
410
411 // Squash if we're not already in a state update mode.
412 if (!thread->trapPending && !thread->inSyscall) {
413 cpu->squashFromTC(thread->readTid());
414 }
415}
416
417template <class Impl>
418void
419O3ThreadContext<Impl>::setPC(uint64_t val)
420{
421 cpu->setPC(val, thread->readTid());
422
423 // Squash if we're not already in a state update mode.
424 if (!thread->trapPending && !thread->inSyscall) {
425 cpu->squashFromTC(thread->readTid());
426 }
427}
428
429template <class Impl>
430void
431O3ThreadContext<Impl>::setNextPC(uint64_t val)
432{
433 cpu->setNextPC(val, thread->readTid());
434
435 // Squash if we're not already in a state update mode.
436 if (!thread->trapPending && !thread->inSyscall) {
437 cpu->squashFromTC(thread->readTid());
438 }
439}
440
441template <class Impl>
442void
443O3ThreadContext<Impl>::setMiscReg(int misc_reg, const MiscReg &val)
444{
445 cpu->setMiscReg(misc_reg, val, thread->readTid());
446
447 // Squash if we're not already in a state update mode.
448 if (!thread->trapPending && !thread->inSyscall) {
449 cpu->squashFromTC(thread->readTid());
450 }
451}
452
453template <class Impl>
454void
455O3ThreadContext<Impl>::setMiscRegWithEffect(int misc_reg,
456 const MiscReg &val)
457{
458 cpu->setMiscRegWithEffect(misc_reg, val, thread->readTid());
459
460 // Squash if we're not already in a state update mode.
461 if (!thread->trapPending && !thread->inSyscall) {
462 cpu->squashFromTC(thread->readTid());
463 }
464}
465
466#if !FULL_SYSTEM
467
468template <class Impl>
469TheISA::IntReg
470O3ThreadContext<Impl>::getSyscallArg(int i)
471{
472 return cpu->getSyscallArg(i, thread->readTid());
473}
474
475template <class Impl>
476void
477O3ThreadContext<Impl>::setSyscallArg(int i, IntReg val)
478{
479 cpu->setSyscallArg(i, val, thread->readTid());
480}
481
482template <class Impl>
483void
484O3ThreadContext<Impl>::setSyscallReturn(SyscallReturn return_value)
485{
486 cpu->setSyscallReturn(return_value, thread->readTid());
487}
488
489#endif // FULL_SYSTEM
490