1/*
2 * Copyright (c) 2010-2012, 2016-2017 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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228const TheISA::VecElem&
229O3ThreadContext<Impl>::readVecElemFlat(const RegIndex& idx,
230 const ElemIndex& elemIndex) const
231{
232 return cpu->readArchVecElem(idx, elemIndex, thread->threadId());
233}
234
235template <class Impl>
236TheISA::CCReg
237O3ThreadContext<Impl>::readCCRegFlat(int reg_idx)
238{
239 return cpu->readArchCCReg(reg_idx, thread->threadId());
240}
241
242template <class Impl>
243void

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272 const ElemIndex& elemIndex, const VecElem& val)
273{
274 cpu->setArchVecElem(idx, elemIndex, val, thread->threadId());
275 conditionalSquash();
276}
277
278template <class Impl>
279void
280O3ThreadContext<Impl>::setCCRegFlat(int reg_idx, TheISA::CCReg val)
281{
282 cpu->setArchCCReg(reg_idx, val, thread->threadId());
283
284 conditionalSquash();
285}
286
287template <class Impl>

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