1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 * Korey Sewell
43 */
44
45#ifndef __CPU_O3_THREAD_CONTEXT_IMPL_HH__
46#define __CPU_O3_THREAD_CONTEXT_IMPL_HH__
47
48#include "arch/kernel_stats.hh"
49#include "arch/registers.hh"
50#include "config/the_isa.hh"
51#include "cpu/o3/thread_context.hh"
52#include "cpu/quiesce_event.hh"
53#include "debug/O3CPU.hh"
54
55template <class Impl>
56FSTranslatingPortProxy&
57O3ThreadContext<Impl>::getVirtProxy()
58{
59 return thread->getVirtProxy();
60}
61
62template <class Impl>
63void
64O3ThreadContext<Impl>::dumpFuncProfile()
65{
66 thread->dumpFuncProfile();
67}
68
69template <class Impl>
70void
71O3ThreadContext<Impl>::takeOverFrom(ThreadContext *old_context)
72{
73 ::takeOverFrom(*this, *old_context);
74 TheISA::Decoder *newDecoder = getDecoderPtr();
75 TheISA::Decoder *oldDecoder = old_context->getDecoderPtr();
76 newDecoder->takeOverFrom(oldDecoder);
77
78 thread->kernelStats = old_context->getKernelStats();
79 thread->funcExeInst = old_context->readFuncExeInst();
80
81 thread->noSquashFromTC = false;
82 thread->trapPending = false;
83}
84
85template <class Impl>
86void
87O3ThreadContext<Impl>::activate(Cycles delay)
88{
89 DPRINTF(O3CPU, "Calling activate on Thread Context %d\n",
90 threadId());
91
92 if (thread->status() == ThreadContext::Active)
93 return;
94
95 thread->lastActivate = curTick();
96 thread->setStatus(ThreadContext::Active);
97
98 // status() == Suspended
99 cpu->activateContext(thread->threadId(), delay);
100}
101
102template <class Impl>
103void
104O3ThreadContext<Impl>::suspend(Cycles delay)
105{
106 DPRINTF(O3CPU, "Calling suspend on Thread Context %d\n",
107 threadId());
108
109 if (thread->status() == ThreadContext::Suspended)
110 return;
111
112 thread->lastActivate = curTick();
113 thread->lastSuspend = curTick();
114
115 thread->setStatus(ThreadContext::Suspended);
116 cpu->suspendContext(thread->threadId());
117}
118
119template <class Impl>
120void
121O3ThreadContext<Impl>::halt(Cycles delay)
122{
123 DPRINTF(O3CPU, "Calling halt on Thread Context %d\n",
124 threadId());
125
126 if (thread->status() == ThreadContext::Halted)
127 return;
128
129 thread->setStatus(ThreadContext::Halted);
130 cpu->haltContext(thread->threadId());
131}
132
133template <class Impl>
134void
135O3ThreadContext<Impl>::regStats(const std::string &name)
136{
137 if (FullSystem) {
138 thread->kernelStats = new TheISA::Kernel::Statistics(cpu->system);
139 thread->kernelStats->regStats(name + ".kern");
140 }
141}
142
143template <class Impl>
144Tick
145O3ThreadContext<Impl>::readLastActivate()
146{
147 return thread->lastActivate;
148}
149
150template <class Impl>
151Tick
152O3ThreadContext<Impl>::readLastSuspend()
153{
154 return thread->lastSuspend;
155}
156
157template <class Impl>
158void
159O3ThreadContext<Impl>::profileClear()
160{
161 thread->profileClear();
162}
163
164template <class Impl>
165void
166O3ThreadContext<Impl>::profileSample()
167{
168 thread->profileSample();
169}
170
171template <class Impl>
172void
173O3ThreadContext<Impl>::copyArchRegs(ThreadContext *tc)
174{
175 // Prevent squashing
176 thread->noSquashFromTC = true;
177 TheISA::copyRegs(tc, this);
178 thread->noSquashFromTC = false;
179
180 if (!FullSystem)
181 this->thread->funcExeInst = tc->readFuncExeInst();
182}
183
184template <class Impl>
185void
186O3ThreadContext<Impl>::clearArchRegs()
187{
188 cpu->isa[thread->threadId()]->clear();
189}
190
191template <class Impl>
192uint64_t
193O3ThreadContext<Impl>::readIntRegFlat(int reg_idx)
194{
195 return cpu->readArchIntReg(reg_idx, thread->threadId());
196}
197
198template <class Impl>
199TheISA::FloatReg
200O3ThreadContext<Impl>::readFloatRegFlat(int reg_idx)
201{
202 return cpu->readArchFloatReg(reg_idx, thread->threadId());
203}
204
205template <class Impl>
206TheISA::FloatRegBits
207O3ThreadContext<Impl>::readFloatRegBitsFlat(int reg_idx)
208{
209 return cpu->readArchFloatRegInt(reg_idx, thread->threadId());
210}
211
212template <class Impl>
213TheISA::CCReg
214O3ThreadContext<Impl>::readCCRegFlat(int reg_idx)
215{
216 return cpu->readArchCCReg(reg_idx, thread->threadId());
217}
218
219template <class Impl>
220void
221O3ThreadContext<Impl>::setIntRegFlat(int reg_idx, uint64_t val)
222{
223 cpu->setArchIntReg(reg_idx, val, thread->threadId());
224
225 conditionalSquash();
226}
227
228template <class Impl>
229void
230O3ThreadContext<Impl>::setFloatRegFlat(int reg_idx, FloatReg val)
231{
232 cpu->setArchFloatReg(reg_idx, val, thread->threadId());
233
234 conditionalSquash();
235}
236
237template <class Impl>
238void
239O3ThreadContext<Impl>::setFloatRegBitsFlat(int reg_idx, FloatRegBits val)
240{
241 cpu->setArchFloatRegInt(reg_idx, val, thread->threadId());
242
243 conditionalSquash();
244}
245
246template <class Impl>
247void
248O3ThreadContext<Impl>::setCCRegFlat(int reg_idx, TheISA::CCReg val)
249{
250 cpu->setArchCCReg(reg_idx, val, thread->threadId());
251
252 conditionalSquash();
253}
254
255template <class Impl>
256void
257O3ThreadContext<Impl>::pcState(const TheISA::PCState &val)
258{
259 cpu->pcState(val, thread->threadId());
260
261 conditionalSquash();
262}
263
264template <class Impl>
265void
266O3ThreadContext<Impl>::pcStateNoRecord(const TheISA::PCState &val)
267{
268 cpu->pcState(val, thread->threadId());
269
270 conditionalSquash();
271}
272
273template <class Impl>
274int
275O3ThreadContext<Impl>::flattenIntIndex(int reg)
276{
277 return cpu->isa[thread->threadId()]->flattenIntIndex(reg);
278}
279
280template <class Impl>
281int
282O3ThreadContext<Impl>::flattenFloatIndex(int reg)
283{
284 return cpu->isa[thread->threadId()]->flattenFloatIndex(reg);
285}
286
287template <class Impl>
288int
289O3ThreadContext<Impl>::flattenCCIndex(int reg)
290{
291 return cpu->isa[thread->threadId()]->flattenCCIndex(reg);
292}
293
294template <class Impl>
295void
296O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
297{
298 cpu->setMiscRegNoEffect(misc_reg, val, thread->threadId());
299
300 conditionalSquash();
301}
302
303#endif//__CPU_O3_THREAD_CONTEXT_IMPL_HH__
304template <class Impl>
305void
306O3ThreadContext<Impl>::setMiscReg(int misc_reg, const MiscReg &val)
307{
308 cpu->setMiscReg(misc_reg, val, thread->threadId());
309
310 conditionalSquash();
311}
312
2 * Copyright (c) 2010-2012 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 * Korey Sewell
43 */
44
45#ifndef __CPU_O3_THREAD_CONTEXT_IMPL_HH__
46#define __CPU_O3_THREAD_CONTEXT_IMPL_HH__
47
48#include "arch/kernel_stats.hh"
49#include "arch/registers.hh"
50#include "config/the_isa.hh"
51#include "cpu/o3/thread_context.hh"
52#include "cpu/quiesce_event.hh"
53#include "debug/O3CPU.hh"
54
55template <class Impl>
56FSTranslatingPortProxy&
57O3ThreadContext<Impl>::getVirtProxy()
58{
59 return thread->getVirtProxy();
60}
61
62template <class Impl>
63void
64O3ThreadContext<Impl>::dumpFuncProfile()
65{
66 thread->dumpFuncProfile();
67}
68
69template <class Impl>
70void
71O3ThreadContext<Impl>::takeOverFrom(ThreadContext *old_context)
72{
73 ::takeOverFrom(*this, *old_context);
74 TheISA::Decoder *newDecoder = getDecoderPtr();
75 TheISA::Decoder *oldDecoder = old_context->getDecoderPtr();
76 newDecoder->takeOverFrom(oldDecoder);
77
78 thread->kernelStats = old_context->getKernelStats();
79 thread->funcExeInst = old_context->readFuncExeInst();
80
81 thread->noSquashFromTC = false;
82 thread->trapPending = false;
83}
84
85template <class Impl>
86void
87O3ThreadContext<Impl>::activate(Cycles delay)
88{
89 DPRINTF(O3CPU, "Calling activate on Thread Context %d\n",
90 threadId());
91
92 if (thread->status() == ThreadContext::Active)
93 return;
94
95 thread->lastActivate = curTick();
96 thread->setStatus(ThreadContext::Active);
97
98 // status() == Suspended
99 cpu->activateContext(thread->threadId(), delay);
100}
101
102template <class Impl>
103void
104O3ThreadContext<Impl>::suspend(Cycles delay)
105{
106 DPRINTF(O3CPU, "Calling suspend on Thread Context %d\n",
107 threadId());
108
109 if (thread->status() == ThreadContext::Suspended)
110 return;
111
112 thread->lastActivate = curTick();
113 thread->lastSuspend = curTick();
114
115 thread->setStatus(ThreadContext::Suspended);
116 cpu->suspendContext(thread->threadId());
117}
118
119template <class Impl>
120void
121O3ThreadContext<Impl>::halt(Cycles delay)
122{
123 DPRINTF(O3CPU, "Calling halt on Thread Context %d\n",
124 threadId());
125
126 if (thread->status() == ThreadContext::Halted)
127 return;
128
129 thread->setStatus(ThreadContext::Halted);
130 cpu->haltContext(thread->threadId());
131}
132
133template <class Impl>
134void
135O3ThreadContext<Impl>::regStats(const std::string &name)
136{
137 if (FullSystem) {
138 thread->kernelStats = new TheISA::Kernel::Statistics(cpu->system);
139 thread->kernelStats->regStats(name + ".kern");
140 }
141}
142
143template <class Impl>
144Tick
145O3ThreadContext<Impl>::readLastActivate()
146{
147 return thread->lastActivate;
148}
149
150template <class Impl>
151Tick
152O3ThreadContext<Impl>::readLastSuspend()
153{
154 return thread->lastSuspend;
155}
156
157template <class Impl>
158void
159O3ThreadContext<Impl>::profileClear()
160{
161 thread->profileClear();
162}
163
164template <class Impl>
165void
166O3ThreadContext<Impl>::profileSample()
167{
168 thread->profileSample();
169}
170
171template <class Impl>
172void
173O3ThreadContext<Impl>::copyArchRegs(ThreadContext *tc)
174{
175 // Prevent squashing
176 thread->noSquashFromTC = true;
177 TheISA::copyRegs(tc, this);
178 thread->noSquashFromTC = false;
179
180 if (!FullSystem)
181 this->thread->funcExeInst = tc->readFuncExeInst();
182}
183
184template <class Impl>
185void
186O3ThreadContext<Impl>::clearArchRegs()
187{
188 cpu->isa[thread->threadId()]->clear();
189}
190
191template <class Impl>
192uint64_t
193O3ThreadContext<Impl>::readIntRegFlat(int reg_idx)
194{
195 return cpu->readArchIntReg(reg_idx, thread->threadId());
196}
197
198template <class Impl>
199TheISA::FloatReg
200O3ThreadContext<Impl>::readFloatRegFlat(int reg_idx)
201{
202 return cpu->readArchFloatReg(reg_idx, thread->threadId());
203}
204
205template <class Impl>
206TheISA::FloatRegBits
207O3ThreadContext<Impl>::readFloatRegBitsFlat(int reg_idx)
208{
209 return cpu->readArchFloatRegInt(reg_idx, thread->threadId());
210}
211
212template <class Impl>
213TheISA::CCReg
214O3ThreadContext<Impl>::readCCRegFlat(int reg_idx)
215{
216 return cpu->readArchCCReg(reg_idx, thread->threadId());
217}
218
219template <class Impl>
220void
221O3ThreadContext<Impl>::setIntRegFlat(int reg_idx, uint64_t val)
222{
223 cpu->setArchIntReg(reg_idx, val, thread->threadId());
224
225 conditionalSquash();
226}
227
228template <class Impl>
229void
230O3ThreadContext<Impl>::setFloatRegFlat(int reg_idx, FloatReg val)
231{
232 cpu->setArchFloatReg(reg_idx, val, thread->threadId());
233
234 conditionalSquash();
235}
236
237template <class Impl>
238void
239O3ThreadContext<Impl>::setFloatRegBitsFlat(int reg_idx, FloatRegBits val)
240{
241 cpu->setArchFloatRegInt(reg_idx, val, thread->threadId());
242
243 conditionalSquash();
244}
245
246template <class Impl>
247void
248O3ThreadContext<Impl>::setCCRegFlat(int reg_idx, TheISA::CCReg val)
249{
250 cpu->setArchCCReg(reg_idx, val, thread->threadId());
251
252 conditionalSquash();
253}
254
255template <class Impl>
256void
257O3ThreadContext<Impl>::pcState(const TheISA::PCState &val)
258{
259 cpu->pcState(val, thread->threadId());
260
261 conditionalSquash();
262}
263
264template <class Impl>
265void
266O3ThreadContext<Impl>::pcStateNoRecord(const TheISA::PCState &val)
267{
268 cpu->pcState(val, thread->threadId());
269
270 conditionalSquash();
271}
272
273template <class Impl>
274int
275O3ThreadContext<Impl>::flattenIntIndex(int reg)
276{
277 return cpu->isa[thread->threadId()]->flattenIntIndex(reg);
278}
279
280template <class Impl>
281int
282O3ThreadContext<Impl>::flattenFloatIndex(int reg)
283{
284 return cpu->isa[thread->threadId()]->flattenFloatIndex(reg);
285}
286
287template <class Impl>
288int
289O3ThreadContext<Impl>::flattenCCIndex(int reg)
290{
291 return cpu->isa[thread->threadId()]->flattenCCIndex(reg);
292}
293
294template <class Impl>
295void
296O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
297{
298 cpu->setMiscRegNoEffect(misc_reg, val, thread->threadId());
299
300 conditionalSquash();
301}
302
303#endif//__CPU_O3_THREAD_CONTEXT_IMPL_HH__
304template <class Impl>
305void
306O3ThreadContext<Impl>::setMiscReg(int misc_reg, const MiscReg &val)
307{
308 cpu->setMiscReg(misc_reg, val, thread->threadId());
309
310 conditionalSquash();
311}
312