1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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59#else
60 assert(getProcessPtr() == old_context->getProcessPtr());
61#endif
62
63 // copy over functional state
64 setStatus(old_context->status());
65 copyArchRegs(old_context);
66 setContextId(old_context->contextId());
67 setThreadId(old_context->threadId());
68
69#if !FULL_SYSTEM
70 thread->funcExeInst = old_context->readFuncExeInst();
71#else
72 EndQuiesceEvent *other_quiesce = old_context->getQuiesceEvent();
73 if (other_quiesce) {
74 // Point the quiesce event's TC at this TC so that it wakes up
75 // the proper CPU.

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91 thread->trapPending = false;
92}
93
94template <class Impl>
95void
96O3ThreadContext<Impl>::activate(int delay)
97{
98 DPRINTF(O3CPU, "Calling activate on Thread Context %d\n",
99 threadId());
100
101 if (thread->status() == ThreadContext::Active)
102 return;
103
104#if FULL_SYSTEM
105 thread->lastActivate = curTick;
106#endif
107
108 if (thread->status() == ThreadContext::Unallocated) {
109 cpu->activateWhenReady(thread->threadId());
110 return;
111 }
112
113 thread->setStatus(ThreadContext::Active);
114
115 // status() == Suspended
116 cpu->activateContext(thread->threadId(), delay);
117}
118
119template <class Impl>
120void
121O3ThreadContext<Impl>::suspend(int delay)
122{
123 DPRINTF(O3CPU, "Calling suspend on Thread Context %d\n",
124 threadId());
125
126 if (thread->status() == ThreadContext::Suspended)
127 return;
128
129#if FULL_SYSTEM
130 thread->lastActivate = curTick;
131 thread->lastSuspend = curTick;
132#endif
133/*
134#if FULL_SYSTEM
135 // Don't change the status from active if there are pending interrupts
136 if (cpu->checkInterrupts()) {
137 assert(status() == ThreadContext::Active);
138 return;
139 }
140#endif
141*/
142 thread->setStatus(ThreadContext::Suspended);
143 cpu->suspendContext(thread->threadId());
144}
145
146template <class Impl>
147void
148O3ThreadContext<Impl>::deallocate(int delay)
149{
150 DPRINTF(O3CPU, "Calling deallocate on Thread Context %d delay %d\n",
151 threadId(), delay);
152
153 if (thread->status() == ThreadContext::Unallocated)
154 return;
155
156 thread->setStatus(ThreadContext::Unallocated);
157 cpu->deallocateContext(thread->threadId(), true, delay);
158}
159
160template <class Impl>
161void
162O3ThreadContext<Impl>::halt(int delay)
163{
164 DPRINTF(O3CPU, "Calling halt on Thread Context %d\n",
165 threadId());
166
167 if (thread->status() == ThreadContext::Halted)
168 return;
169
170 thread->setStatus(ThreadContext::Halted);
171 cpu->haltContext(thread->threadId());
172}
173
174template <class Impl>
175void
176O3ThreadContext<Impl>::regStats(const std::string &name)
177{
178#if FULL_SYSTEM
179 thread->kernelStats = new TheISA::Kernel::Statistics(cpu->system);

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241}
242
243template <class Impl>
244void
245O3ThreadContext<Impl>::copyArchRegs(ThreadContext *tc)
246{
247 // This function will mess things up unless the ROB is empty and
248 // there are no instructions in the pipeline.
249 unsigned tid = thread->threadId();
250 PhysRegIndex renamed_reg;
251
252 // First loop through the integer registers.
253 for (int i = 0; i < TheISA::NumIntRegs; ++i) {
254 renamed_reg = cpu->renameMap[tid].lookup(i);
255
256 DPRINTF(O3CPU, "Copying over register %i, had data %lli, "
257 "now has data %lli.\n",

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288O3ThreadContext<Impl>::clearArchRegs()
289{}
290
291template <class Impl>
292uint64_t
293O3ThreadContext<Impl>::readIntReg(int reg_idx)
294{
295 reg_idx = TheISA::flattenIntIndex(this, reg_idx);
296 return cpu->readArchIntReg(reg_idx, thread->threadId());
297}
298
299template <class Impl>
300TheISA::FloatReg
301O3ThreadContext<Impl>::readFloatReg(int reg_idx, int width)
302{
303 reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
304 switch(width) {
305 case 32:
306 return cpu->readArchFloatRegSingle(reg_idx, thread->threadId());
307 case 64:
308 return cpu->readArchFloatRegDouble(reg_idx, thread->threadId());
309 default:
310 panic("Unsupported width!");
311 return 0;
312 }
313}
314
315template <class Impl>
316TheISA::FloatReg
317O3ThreadContext<Impl>::readFloatReg(int reg_idx)
318{
319 reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
320 return cpu->readArchFloatRegSingle(reg_idx, thread->threadId());
321}
322
323template <class Impl>
324TheISA::FloatRegBits
325O3ThreadContext<Impl>::readFloatRegBits(int reg_idx, int width)
326{
327 DPRINTF(Fault, "Reading floatint register through the TC!\n");
328 reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
329 return cpu->readArchFloatRegInt(reg_idx, thread->threadId());
330}
331
332template <class Impl>
333TheISA::FloatRegBits
334O3ThreadContext<Impl>::readFloatRegBits(int reg_idx)
335{
336 reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
337 return cpu->readArchFloatRegInt(reg_idx, thread->threadId());
338}
339
340template <class Impl>
341void
342O3ThreadContext<Impl>::setIntReg(int reg_idx, uint64_t val)
343{
344 reg_idx = TheISA::flattenIntIndex(this, reg_idx);
345 cpu->setArchIntReg(reg_idx, val, thread->threadId());
346
347 // Squash if we're not already in a state update mode.
348 if (!thread->trapPending && !thread->inSyscall) {
349 cpu->squashFromTC(thread->threadId());
350 }
351}
352
353template <class Impl>
354void
355O3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val, int width)
356{
357 reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
358 switch(width) {
359 case 32:
360 cpu->setArchFloatRegSingle(reg_idx, val, thread->threadId());
361 break;
362 case 64:
363 cpu->setArchFloatRegDouble(reg_idx, val, thread->threadId());
364 break;
365 }
366
367 // Squash if we're not already in a state update mode.
368 if (!thread->trapPending && !thread->inSyscall) {
369 cpu->squashFromTC(thread->threadId());
370 }
371}
372
373template <class Impl>
374void
375O3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val)
376{
377 reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
378 cpu->setArchFloatRegSingle(reg_idx, val, thread->threadId());
379
380 if (!thread->trapPending && !thread->inSyscall) {
381 cpu->squashFromTC(thread->threadId());
382 }
383}
384
385template <class Impl>
386void
387O3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val,
388 int width)
389{
390 DPRINTF(Fault, "Setting floatint register through the TC!\n");
391 reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
392 cpu->setArchFloatRegInt(reg_idx, val, thread->threadId());
393
394 // Squash if we're not already in a state update mode.
395 if (!thread->trapPending && !thread->inSyscall) {
396 cpu->squashFromTC(thread->threadId());
397 }
398}
399
400template <class Impl>
401void
402O3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
403{
404 reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
405 cpu->setArchFloatRegInt(reg_idx, val, thread->threadId());
406
407 // Squash if we're not already in a state update mode.
408 if (!thread->trapPending && !thread->inSyscall) {
409 cpu->squashFromTC(thread->threadId());
410 }
411}
412
413template <class Impl>
414void
415O3ThreadContext<Impl>::setPC(uint64_t val)
416{
417 cpu->setPC(val, thread->threadId());
418
419 // Squash if we're not already in a state update mode.
420 if (!thread->trapPending && !thread->inSyscall) {
421 cpu->squashFromTC(thread->threadId());
422 }
423}
424
425template <class Impl>
426void
427O3ThreadContext<Impl>::setNextPC(uint64_t val)
428{
429 cpu->setNextPC(val, thread->threadId());
430
431 // Squash if we're not already in a state update mode.
432 if (!thread->trapPending && !thread->inSyscall) {
433 cpu->squashFromTC(thread->threadId());
434 }
435}
436
437template <class Impl>
438void
439O3ThreadContext<Impl>::setMicroPC(uint64_t val)
440{
441 cpu->setMicroPC(val, thread->threadId());
442
443 // Squash if we're not already in a state update mode.
444 if (!thread->trapPending && !thread->inSyscall) {
445 cpu->squashFromTC(thread->threadId());
446 }
447}
448
449template <class Impl>
450void
451O3ThreadContext<Impl>::setNextMicroPC(uint64_t val)
452{
453 cpu->setNextMicroPC(val, thread->threadId());
454
455 // Squash if we're not already in a state update mode.
456 if (!thread->trapPending && !thread->inSyscall) {
457 cpu->squashFromTC(thread->threadId());
458 }
459}
460
461template <class Impl>
462void
463O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
464{
465 cpu->setMiscRegNoEffect(misc_reg, val, thread->threadId());
466
467 // Squash if we're not already in a state update mode.
468 if (!thread->trapPending && !thread->inSyscall) {
469 cpu->squashFromTC(thread->threadId());
470 }
471}
472
473template <class Impl>
474void
475O3ThreadContext<Impl>::setMiscReg(int misc_reg,
476 const MiscReg &val)
477{
478 cpu->setMiscReg(misc_reg, val, thread->threadId());
479
480 // Squash if we're not already in a state update mode.
481 if (!thread->trapPending && !thread->inSyscall) {
482 cpu->squashFromTC(thread->threadId());
483 }
484}
485
486#if !FULL_SYSTEM
487
488template <class Impl>
489TheISA::IntReg
490O3ThreadContext<Impl>::getSyscallArg(int i)
491{
492 return cpu->getSyscallArg(i, thread->threadId());
493}
494
495template <class Impl>
496void
497O3ThreadContext<Impl>::setSyscallArg(int i, IntReg val)
498{
499 cpu->setSyscallArg(i, val, thread->threadId());
500}
501
502template <class Impl>
503void
504O3ThreadContext<Impl>::setSyscallReturn(SyscallReturn return_value)
505{
506 cpu->setSyscallReturn(return_value, thread->threadId());
507}
508
509#endif // FULL_SYSTEM
510