1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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27 * 28 * Authors: Kevin Lim |
29 */ 30
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29#ifndef __CPU_O3_STORE_SET_HH__
30#define __CPU_O3_STORE_SET_HH__
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31#ifndef __CPU_O3_CPU_STORE_SET_HH__ 32#define __CPU_O3_CPU_STORE_SET_HH__ |
33
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32#include <list>
33#include <map>
34#include <utility>
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34#include <vector> 35 36#include "arch/isa_traits.hh" 37#include "cpu/inst_seq.hh" 38
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40struct ltseqnum {
41 bool operator()(const InstSeqNum &lhs, const InstSeqNum &rhs) const
42 {
43 return lhs > rhs;
44 }
45};
46
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39class StoreSet 40{ 41 public: 42 typedef unsigned SSID; 43 44 public:
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53 StoreSet() { };
54
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45 StoreSet(int SSIT_size, int LFST_size); 46
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57 ~StoreSet();
58
59 void init(int SSIT_size, int LFST_size);
60
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47 void violation(Addr store_PC, Addr load_PC); 48 49 void insertLoad(Addr load_PC, InstSeqNum load_seq_num); 50
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65 void insertStore(Addr store_PC, InstSeqNum store_seq_num,
66 unsigned tid);
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51 void insertStore(Addr store_PC, InstSeqNum store_seq_num); |
52 53 InstSeqNum checkInst(Addr PC); 54 55 void issued(Addr issued_PC, InstSeqNum issued_seq_num, bool is_store); 56
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72 void squash(InstSeqNum squashed_num, unsigned tid);
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57 void squash(InstSeqNum squashed_num); |
58 59 void clear(); 60 61 private: 62 inline int calcIndex(Addr PC)
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78 { return (PC >> offsetBits) & indexMask; }
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63 { return (PC >> offset_bits) & index_mask; } |
64 65 inline SSID calcSSID(Addr PC)
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81 { return ((PC ^ (PC >> 10)) % LFSTSize); }
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66 { return ((PC ^ (PC >> 10)) % LFST_size); } |
67
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83 std::vector<SSID> SSIT;
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68 SSID *SSIT; |
69 70 std::vector<bool> validSSIT; 71
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87 std::vector<InstSeqNum> LFST;
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72 InstSeqNum *LFST; |
73 74 std::vector<bool> validLFST; 75
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91 std::map<InstSeqNum, int, ltseqnum> storeList;
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76 int *SSCounters; |
77
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93 typedef std::map<InstSeqNum, int, ltseqnum>::iterator SeqNumMapIt;
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78 int SSIT_size; |
79
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95 int SSITSize;
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80 int LFST_size; |
81
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97 int LFSTSize;
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82 int index_mask; |
83
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99 int indexMask;
100
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84 // HACK: Hardcoded for now.
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102 int offsetBits;
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85 int offset_bits; |
86}; 87
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105#endif // __CPU_O3_STORE_SET_HH__
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88#endif // __CPU_O3_CPU_STORE_SET_HH__ |
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