1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
29#ifndef __CPU_O3_STORE_SET_HH__
30#define __CPU_O3_STORE_SET_HH__
31#ifndef __CPU_O3_CPU_STORE_SET_HH__
32#define __CPU_O3_CPU_STORE_SET_HH__
33
32#include <list>
33#include <map>
34#include <utility>
34#include <vector>
35
36#include "arch/isa_traits.hh"
37#include "cpu/inst_seq.hh"
38
40struct ltseqnum {
41 bool operator()(const InstSeqNum &lhs, const InstSeqNum &rhs) const
42 {
43 return lhs > rhs;
44 }
45};
46
39class StoreSet
40{
41 public:
42 typedef unsigned SSID;
43
44 public:
53 StoreSet() { };
54
45 StoreSet(int SSIT_size, int LFST_size);
46
57 ~StoreSet();
58
59 void init(int SSIT_size, int LFST_size);
60
47 void violation(Addr store_PC, Addr load_PC);
48
49 void insertLoad(Addr load_PC, InstSeqNum load_seq_num);
50
65 void insertStore(Addr store_PC, InstSeqNum store_seq_num,
66 unsigned tid);
51 void insertStore(Addr store_PC, InstSeqNum store_seq_num);
52
53 InstSeqNum checkInst(Addr PC);
54
55 void issued(Addr issued_PC, InstSeqNum issued_seq_num, bool is_store);
56
72 void squash(InstSeqNum squashed_num, unsigned tid);
57 void squash(InstSeqNum squashed_num);
58
59 void clear();
60
61 private:
62 inline int calcIndex(Addr PC)
78 { return (PC >> offsetBits) & indexMask; }
63 { return (PC >> offset_bits) & index_mask; }
64
65 inline SSID calcSSID(Addr PC)
81 { return ((PC ^ (PC >> 10)) % LFSTSize); }
66 { return ((PC ^ (PC >> 10)) % LFST_size); }
67
83 std::vector<SSID> SSIT;
68 SSID *SSIT;
69
70 std::vector<bool> validSSIT;
71
87 std::vector<InstSeqNum> LFST;
72 InstSeqNum *LFST;
73
74 std::vector<bool> validLFST;
75
91 std::map<InstSeqNum, int, ltseqnum> storeList;
76 int *SSCounters;
77
93 typedef std::map<InstSeqNum, int, ltseqnum>::iterator SeqNumMapIt;
78 int SSIT_size;
79
95 int SSITSize;
80 int LFST_size;
81
97 int LFSTSize;
82 int index_mask;
83
99 int indexMask;
100
84 // HACK: Hardcoded for now.
102 int offsetBits;
85 int offset_bits;
86};
87
105#endif // __CPU_O3_STORE_SET_HH__
88#endif // __CPU_O3_CPU_STORE_SET_HH__