1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28
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29#ifndef __CPU_O3_CPU_STORE_SET_HH__
30#define __CPU_O3_CPU_STORE_SET_HH__
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29#ifndef __CPU_O3_STORE_SET_HH__ 30#define __CPU_O3_STORE_SET_HH__ |
31
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32#include <list> 33#include <map> 34#include <utility> |
35#include <vector> 36 37#include "arch/isa_traits.hh" 38#include "cpu/inst_seq.hh" 39
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40struct ltseqnum { 41 bool operator()(const InstSeqNum &lhs, const InstSeqNum &rhs) const 42 { 43 return lhs > rhs; 44 } 45}; 46 |
47class StoreSet 48{ 49 public: 50 typedef unsigned SSID; 51 52 public:
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53 StoreSet() { }; 54 |
55 StoreSet(int SSIT_size, int LFST_size); 56
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57 ~StoreSet(); 58 59 void init(int SSIT_size, int LFST_size); 60 |
61 void violation(Addr store_PC, Addr load_PC); 62 63 void insertLoad(Addr load_PC, InstSeqNum load_seq_num); 64
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49 void insertStore(Addr store_PC, InstSeqNum store_seq_num);
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65 void insertStore(Addr store_PC, InstSeqNum store_seq_num, 66 unsigned tid); |
67 68 InstSeqNum checkInst(Addr PC); 69 70 void issued(Addr issued_PC, InstSeqNum issued_seq_num, bool is_store); 71
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55 void squash(InstSeqNum squashed_num);
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72 void squash(InstSeqNum squashed_num, unsigned tid); |
73 74 void clear(); 75 76 private: 77 inline int calcIndex(Addr PC)
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61 { return (PC >> offset_bits) & index_mask; }
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78 { return (PC >> offsetBits) & indexMask; } |
79 80 inline SSID calcSSID(Addr PC)
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64 { return ((PC ^ (PC >> 10)) % LFST_size); }
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81 { return ((PC ^ (PC >> 10)) % LFSTSize); } |
82
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66 SSID *SSIT;
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83 std::vector<SSID> SSIT; |
84 85 std::vector<bool> validSSIT; 86
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70 InstSeqNum *LFST;
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87 std::vector<InstSeqNum> LFST; |
88 89 std::vector<bool> validLFST; 90
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74 int *SSCounters;
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91 std::map<InstSeqNum, int, ltseqnum> storeList; |
92
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76 int SSIT_size;
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93 typedef std::map<InstSeqNum, int, ltseqnum>::iterator SeqNumMapIt; |
94
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78 int LFST_size;
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95 int SSITSize; |
96
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80 int index_mask;
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97 int LFSTSize; |
98
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99 int indexMask; 100 |
101 // HACK: Hardcoded for now.
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83 int offset_bits;
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102 int offsetBits; |
103}; 104
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86#endif // __CPU_O3_CPU_STORE_SET_HH__
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105#endif // __CPU_O3_STORE_SET_HH__ |
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