1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 */ 30 31#ifndef __CPU_O3_STORE_SET_HH__ 32#define __CPU_O3_STORE_SET_HH__ 33 34#include <list> 35#include <map> 36#include <utility> 37#include <vector> 38 39#include "arch/isa_traits.hh" 40#include "cpu/inst_seq.hh" 41 42struct ltseqnum { 43 bool operator()(const InstSeqNum &lhs, const InstSeqNum &rhs) const 44 { 45 return lhs > rhs; 46 } 47}; 48
| 1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 */ 30 31#ifndef __CPU_O3_STORE_SET_HH__ 32#define __CPU_O3_STORE_SET_HH__ 33 34#include <list> 35#include <map> 36#include <utility> 37#include <vector> 38 39#include "arch/isa_traits.hh" 40#include "cpu/inst_seq.hh" 41 42struct ltseqnum { 43 bool operator()(const InstSeqNum &lhs, const InstSeqNum &rhs) const 44 { 45 return lhs > rhs; 46 } 47}; 48
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| 49/** 50 * Implements a store set predictor for determining if memory 51 * instructions are dependent upon each other. See paper "Memory 52 * Dependence Prediction using Store Sets" by Chrysos and Emer. SSID 53 * stands for Store Set ID, SSIT stands for Store Set ID Table, and 54 * LFST is Last Fetched Store Table. 55 */
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49class StoreSet 50{ 51 public: 52 typedef unsigned SSID; 53 54 public:
| 56class StoreSet 57{ 58 public: 59 typedef unsigned SSID; 60 61 public:
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| 62 /** Default constructor. init() must be called prior to use. */
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55 StoreSet() { }; 56
| 63 StoreSet() { }; 64
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| 65 /** Creates store set predictor with given table sizes. */
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57 StoreSet(int SSIT_size, int LFST_size); 58
| 66 StoreSet(int SSIT_size, int LFST_size); 67
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| 68 /** Default destructor. */
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59 ~StoreSet(); 60
| 69 ~StoreSet(); 70
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| 71 /** Initializes the store set predictor with the given table sizes. */
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61 void init(int SSIT_size, int LFST_size); 62
| 72 void init(int SSIT_size, int LFST_size); 73
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| 74 /** Records a memory ordering violation between the younger load 75 * and the older store. */
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63 void violation(Addr store_PC, Addr load_PC); 64
| 76 void violation(Addr store_PC, Addr load_PC); 77
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| 78 /** Inserts a load into the store set predictor. This does nothing but 79 * is included in case other predictors require a similar function. 80 */
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65 void insertLoad(Addr load_PC, InstSeqNum load_seq_num); 66
| 81 void insertLoad(Addr load_PC, InstSeqNum load_seq_num); 82
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| 83 /** Inserts a store into the store set predictor. Updates the 84 * LFST if the store has a valid SSID. */
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67 void insertStore(Addr store_PC, InstSeqNum store_seq_num, 68 unsigned tid); 69
| 85 void insertStore(Addr store_PC, InstSeqNum store_seq_num, 86 unsigned tid); 87
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| 88 /** Checks if the instruction with the given PC is dependent upon 89 * any store. @return Returns the sequence number of the store 90 * instruction this PC is dependent upon. Returns 0 if none. 91 */
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70 InstSeqNum checkInst(Addr PC); 71
| 92 InstSeqNum checkInst(Addr PC); 93
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| 94 /** Records this PC/sequence number as issued. */
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72 void issued(Addr issued_PC, InstSeqNum issued_seq_num, bool is_store); 73
| 95 void issued(Addr issued_PC, InstSeqNum issued_seq_num, bool is_store); 96
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| 97 /** Squashes for a specific thread until the given sequence number. */
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74 void squash(InstSeqNum squashed_num, unsigned tid); 75
| 98 void squash(InstSeqNum squashed_num, unsigned tid); 99
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| 100 /** Resets all tables. */
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76 void clear(); 77
| 101 void clear(); 102
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| 103 /** Debug function to dump the contents of the store list. */ 104 void dump(); 105
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78 private:
| 106 private:
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| 107 /** Calculates the index into the SSIT based on the PC. */
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79 inline int calcIndex(Addr PC) 80 { return (PC >> offsetBits) & indexMask; } 81
| 108 inline int calcIndex(Addr PC) 109 { return (PC >> offsetBits) & indexMask; } 110
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| 111 /** Calculates a Store Set ID based on the PC. */
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82 inline SSID calcSSID(Addr PC) 83 { return ((PC ^ (PC >> 10)) % LFSTSize); } 84
| 112 inline SSID calcSSID(Addr PC) 113 { return ((PC ^ (PC >> 10)) % LFSTSize); } 114
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| 115 /** The Store Set ID Table. */
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85 std::vector<SSID> SSIT; 86
| 116 std::vector<SSID> SSIT; 117
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| 118 /** Bit vector to tell if the SSIT has a valid entry. */
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87 std::vector<bool> validSSIT; 88
| 119 std::vector<bool> validSSIT; 120
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| 121 /** Last Fetched Store Table. */
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89 std::vector<InstSeqNum> LFST; 90
| 122 std::vector<InstSeqNum> LFST; 123
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| 124 /** Bit vector to tell if the LFST has a valid entry. */
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91 std::vector<bool> validLFST; 92
| 125 std::vector<bool> validLFST; 126
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| 127 /** Map of stores that have been inserted into the store set, but 128 * not yet issued or squashed. 129 */
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93 std::map<InstSeqNum, int, ltseqnum> storeList; 94 95 typedef std::map<InstSeqNum, int, ltseqnum>::iterator SeqNumMapIt; 96
| 130 std::map<InstSeqNum, int, ltseqnum> storeList; 131 132 typedef std::map<InstSeqNum, int, ltseqnum>::iterator SeqNumMapIt; 133
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| 134 /** Store Set ID Table size, in entries. */
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97 int SSITSize; 98
| 135 int SSITSize; 136
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| 137 /** Last Fetched Store Table size, in entries. */
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99 int LFSTSize; 100
| 138 int LFSTSize; 139
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| 140 /** Mask to obtain the index. */
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101 int indexMask; 102 103 // HACK: Hardcoded for now. 104 int offsetBits; 105}; 106 107#endif // __CPU_O3_STORE_SET_HH__
| 141 int indexMask; 142 143 // HACK: Hardcoded for now. 144 int offsetBits; 145}; 146 147#endif // __CPU_O3_STORE_SET_HH__
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