1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
| 1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
|
31#ifndef __CPU_O3_CPU_STORE_SET_HH__
32#define __CPU_O3_CPU_STORE_SET_HH__
| 31#ifndef __CPU_O3_STORE_SET_HH__
32#define __CPU_O3_STORE_SET_HH__
|
33
| 33
|
| 34#include <list>
35#include <map>
36#include <utility>
|
34#include <vector>
35
36#include "arch/isa_traits.hh"
37#include "cpu/inst_seq.hh"
38
| 37#include <vector>
38
39#include "arch/isa_traits.hh"
40#include "cpu/inst_seq.hh"
41
|
| 42struct ltseqnum {
43 bool operator()(const InstSeqNum &lhs, const InstSeqNum &rhs) const
44 {
45 return lhs > rhs;
46 }
47};
48
|
39class StoreSet
40{
41 public:
42 typedef unsigned SSID;
43
44 public:
| 49class StoreSet
50{
51 public:
52 typedef unsigned SSID;
53
54 public:
|
| 55 StoreSet() { };
56
|
45 StoreSet(int SSIT_size, int LFST_size);
46
| 57 StoreSet(int SSIT_size, int LFST_size);
58
|
| 59 ~StoreSet();
60
61 void init(int SSIT_size, int LFST_size);
62
|
47 void violation(Addr store_PC, Addr load_PC);
48
49 void insertLoad(Addr load_PC, InstSeqNum load_seq_num);
50
| 63 void violation(Addr store_PC, Addr load_PC);
64
65 void insertLoad(Addr load_PC, InstSeqNum load_seq_num);
66
|
51 void insertStore(Addr store_PC, InstSeqNum store_seq_num);
| 67 void insertStore(Addr store_PC, InstSeqNum store_seq_num,
68 unsigned tid);
|
52
53 InstSeqNum checkInst(Addr PC);
54
55 void issued(Addr issued_PC, InstSeqNum issued_seq_num, bool is_store);
56
| 69
70 InstSeqNum checkInst(Addr PC);
71
72 void issued(Addr issued_PC, InstSeqNum issued_seq_num, bool is_store);
73
|
57 void squash(InstSeqNum squashed_num);
| 74 void squash(InstSeqNum squashed_num, unsigned tid);
|
58
59 void clear();
60
61 private:
62 inline int calcIndex(Addr PC)
| 75
76 void clear();
77
78 private:
79 inline int calcIndex(Addr PC)
|
63 { return (PC >> offset_bits) & index_mask; }
| 80 { return (PC >> offsetBits) & indexMask; }
|
64
65 inline SSID calcSSID(Addr PC)
| 81
82 inline SSID calcSSID(Addr PC)
|
66 { return ((PC ^ (PC >> 10)) % LFST_size); }
| 83 { return ((PC ^ (PC >> 10)) % LFSTSize); }
|
67
| 84
|
68 SSID *SSIT;
| 85 std::vector<SSID> SSIT;
|
69
70 std::vector<bool> validSSIT;
71
| 86
87 std::vector<bool> validSSIT;
88
|
72 InstSeqNum *LFST;
| 89 std::vector<InstSeqNum> LFST;
|
73
74 std::vector<bool> validLFST;
75
| 90
91 std::vector<bool> validLFST;
92
|
76 int *SSCounters;
| 93 std::map<InstSeqNum, int, ltseqnum> storeList;
|
77
| 94
|
78 int SSIT_size;
| 95 typedef std::map<InstSeqNum, int, ltseqnum>::iterator SeqNumMapIt;
|
79
| 96
|
80 int LFST_size;
| 97 int SSITSize;
|
81
| 98
|
82 int index_mask;
| 99 int LFSTSize;
|
83
| 100
|
| 101 int indexMask;
102
|
84 // HACK: Hardcoded for now.
| 103 // HACK: Hardcoded for now.
|
85 int offset_bits;
| 104 int offsetBits;
|
86};
87
| 105};
106
|
88#endif // __CPU_O3_CPU_STORE_SET_HH__
| 107#endif // __CPU_O3_STORE_SET_HH__
|
| |