1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28
| 1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28
|
29#ifndef __CPU_O3_CPU_STORE_SET_HH__ 30#define __CPU_O3_CPU_STORE_SET_HH__
| 29#ifndef __CPU_O3_STORE_SET_HH__ 30#define __CPU_O3_STORE_SET_HH__
|
31
| 31
|
| 32#include <list> 33#include <map> 34#include <utility>
|
32#include <vector> 33 34#include "arch/isa_traits.hh" 35#include "cpu/inst_seq.hh" 36
| 35#include <vector> 36 37#include "arch/isa_traits.hh" 38#include "cpu/inst_seq.hh" 39
|
| 40struct ltseqnum { 41 bool operator()(const InstSeqNum &lhs, const InstSeqNum &rhs) const 42 { 43 return lhs > rhs; 44 } 45}; 46
|
37class StoreSet 38{ 39 public: 40 typedef unsigned SSID; 41 42 public:
| 47class StoreSet 48{ 49 public: 50 typedef unsigned SSID; 51 52 public:
|
| 53 StoreSet() { }; 54
|
43 StoreSet(int SSIT_size, int LFST_size); 44
| 55 StoreSet(int SSIT_size, int LFST_size); 56
|
| 57 ~StoreSet(); 58 59 void init(int SSIT_size, int LFST_size); 60
|
45 void violation(Addr store_PC, Addr load_PC); 46 47 void insertLoad(Addr load_PC, InstSeqNum load_seq_num); 48
| 61 void violation(Addr store_PC, Addr load_PC); 62 63 void insertLoad(Addr load_PC, InstSeqNum load_seq_num); 64
|
49 void insertStore(Addr store_PC, InstSeqNum store_seq_num);
| 65 void insertStore(Addr store_PC, InstSeqNum store_seq_num, 66 unsigned tid);
|
50 51 InstSeqNum checkInst(Addr PC); 52 53 void issued(Addr issued_PC, InstSeqNum issued_seq_num, bool is_store); 54
| 67 68 InstSeqNum checkInst(Addr PC); 69 70 void issued(Addr issued_PC, InstSeqNum issued_seq_num, bool is_store); 71
|
55 void squash(InstSeqNum squashed_num);
| 72 void squash(InstSeqNum squashed_num, unsigned tid);
|
56 57 void clear(); 58 59 private: 60 inline int calcIndex(Addr PC)
| 73 74 void clear(); 75 76 private: 77 inline int calcIndex(Addr PC)
|
61 { return (PC >> offset_bits) & index_mask; }
| 78 { return (PC >> offsetBits) & indexMask; }
|
62 63 inline SSID calcSSID(Addr PC)
| 79 80 inline SSID calcSSID(Addr PC)
|
64 { return ((PC ^ (PC >> 10)) % LFST_size); }
| 81 { return ((PC ^ (PC >> 10)) % LFSTSize); }
|
65
| 82
|
66 SSID *SSIT;
| 83 std::vector<SSID> SSIT;
|
67 68 std::vector<bool> validSSIT; 69
| 84 85 std::vector<bool> validSSIT; 86
|
70 InstSeqNum *LFST;
| 87 std::vector<InstSeqNum> LFST;
|
71 72 std::vector<bool> validLFST; 73
| 88 89 std::vector<bool> validLFST; 90
|
74 int *SSCounters;
| 91 std::map<InstSeqNum, int, ltseqnum> storeList;
|
75
| 92
|
76 int SSIT_size;
| 93 typedef std::map<InstSeqNum, int, ltseqnum>::iterator SeqNumMapIt;
|
77
| 94
|
78 int LFST_size;
| 95 int SSITSize;
|
79
| 96
|
80 int index_mask;
| 97 int LFSTSize;
|
81
| 98
|
| 99 int indexMask; 100
|
82 // HACK: Hardcoded for now.
| 101 // HACK: Hardcoded for now.
|
83 int offset_bits;
| 102 int offsetBits;
|
84}; 85
| 103}; 104
|
86#endif // __CPU_O3_CPU_STORE_SET_HH__
| 105#endif // __CPU_O3_STORE_SET_HH__
|
| |