1/* |
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan |
3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the --- 8 unchanged lines hidden (view full) --- 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 * 28 * Authors: Kevin Lim |
29 */ 30 |
31#ifndef __CPU_O3_CPU_ROB_IMPL_HH__ 32#define __CPU_O3_CPU_ROB_IMPL_HH__ 33 |
34#include "config/full_system.hh" 35#include "cpu/o3/rob.hh" 36 |
37template <class Impl> |
38ROB<Impl>::ROB(unsigned _numEntries, unsigned _squashWidth) |
39 : numEntries(_numEntries), 40 squashWidth(_squashWidth), 41 numInstsInROB(0), |
42 squashedSeqNum(0) |
43{ |
44 doneSquashing = true; |
45} 46 47template <class Impl> |
48void 49ROB<Impl>::setCPU(FullCPU *cpu_ptr) 50{ 51 cpu = cpu_ptr; 52 |
53 // Set the tail to the beginning of the CPU instruction list so that 54 // upon the first instruction being inserted into the ROB, the tail 55 // iterator can simply be incremented. 56 tail = cpu->instList.begin(); |
57 |
58 // Set the squash iterator to the end of the instruction list. 59 squashIt = cpu->instList.end(); |
60} 61 62template <class Impl> |
63int 64ROB<Impl>::countInsts() |
65{ |
66 // Start at 1; if the tail matches cpu->instList.begin(), then there is 67 // one inst in the ROB. 68 int return_val = 1; |
69 |
70 // There are quite a few special cases. Do not use this function other 71 // than for debugging purposes. 72 if (cpu->instList.begin() == cpu->instList.end()) { 73 // In this case there are no instructions in the list. The ROB 74 // must be empty. 75 return 0; 76 } else if (tail == cpu->instList.end()) { 77 // In this case, the tail is not yet pointing to anything valid. 78 // The ROB must be empty. 79 return 0; |
80 } |
81 |
82 // Iterate through the ROB from the head to the tail, counting the 83 // entries. 84 for (InstIt_t i = cpu->instList.begin(); i != tail; ++i) 85 { 86 assert(i != cpu->instList.end()); 87 ++return_val; |
88 } |
89 |
90 return return_val; |
91 |
92 // Because the head won't be tracked properly until the ROB gets the 93 // first instruction, and any time that the ROB is empty and has not 94 // yet gotten the instruction, this function doesn't work. 95// return numInstsInROB; |
96} 97 98template <class Impl> |
99void 100ROB<Impl>::insertInst(DynInstPtr &inst) 101{ |
102 // Make sure we have the right number of instructions. 103 assert(numInstsInROB == countInsts()); 104 // Make sure the instruction is valid. |
105 assert(inst); 106 |
107 DPRINTF(ROB, "ROB: Adding inst PC %#x to the ROB.\n", inst->readPC()); |
108 |
109 // If the ROB is full then exit. |
110 assert(numInstsInROB != numEntries); 111 |
112 ++numInstsInROB; |
113 |
114 // Increment the tail iterator, moving it one instruction back. 115 // There is a special case if the ROB was empty prior to this insertion, 116 // in which case the tail will be pointing at instList.end(). If that 117 // happens, then reset the tail to the beginning of the list. 118 if (tail != cpu->instList.end()) { 119 ++tail; 120 } else { 121 tail = cpu->instList.begin(); |
122 } 123 |
124 // Make sure the tail iterator is actually pointing at the instruction 125 // added. |
126 assert((*tail) == inst); 127 |
128 DPRINTF(ROB, "ROB: Now has %d instructions.\n", numInstsInROB); 129 |
130} 131 132// Whatever calls this function needs to ensure that it properly frees up 133// registers prior to this function. |
134template <class Impl> 135void 136ROB<Impl>::retireHead() 137{ |
138 assert(numInstsInROB == countInsts()); |
139 assert(numInstsInROB > 0); 140 |
141 // Get the head ROB instruction. |
142 DynInstPtr head_inst = cpu->instList.front(); |
143 |
144 // Make certain this can retire. |
145 assert(head_inst->readyToCommit()); 146 |
147 DPRINTF(ROB, "ROB: Retiring head instruction of the ROB, " 148 "instruction PC %#x, seq num %i\n", head_inst->readPC(), |
149 head_inst->seqNum); 150 |
151 // Keep track of how many instructions are in the ROB. |
152 --numInstsInROB; |
153 |
154 // Tell CPU to remove the instruction from the list of instructions. 155 // A special case is needed if the instruction being retired is the 156 // only instruction in the ROB; otherwise the tail iterator will become 157 // invalidated. |
158 cpu->removeFrontInst(head_inst); |
159 |
160 if (numInstsInROB == 0) { 161 tail = cpu->instList.end(); |
162 } |
163} 164 165template <class Impl> 166bool |
167ROB<Impl>::isHeadReady() |
168{ |
169 if (numInstsInROB != 0) { 170 return cpu->instList.front()->readyToCommit(); |
171 } 172 173 return false; 174} 175 176template <class Impl> 177unsigned 178ROB<Impl>::numFreeEntries() 179{ |
180 assert(numInstsInROB == countInsts()); |
181 182 return numEntries - numInstsInROB; 183} 184 185template <class Impl> |
186void |
187ROB |
188{ |
189 DPRINTF(ROB, "ROB: Squashing instructions.\n"); |
190 |
191 assert(squashIt != cpu->instList.end()); |
192 |
193 for (int numSquashed = 0; |
194 numSquashed < squashWidth && (*squashIt)->seqNum != squashedSeqNum; |
195 ++numSquashed) 196 { |
197 // Ensure that the instruction is younger. 198 assert((*squashIt)->seqNum > squashedSeqNum); |
199 |
200 DPRINTF(ROB, "ROB: Squashing instruction PC %#x, seq num %i.\n", 201 (*squashIt)->readPC(), (*squashIt)->seqNum); 202 |
203 // Mark the instruction as squashed, and ready to commit so that 204 // it can drain out of the pipeline. |
205 (*squashIt)->setSquashed(); |
206 |
207 (*squashIt)->setCanCommit(); |
208 |
209 // Special case for when squashing due to a syscall. It's possible 210 // that the squash happened after the head instruction was already 211 // committed, meaning that (*squashIt)->seqNum != squashedSeqNum 212 // will never be false. Normally the squash would never be able 213 // to go past the head of the ROB; in this case it might, so it 214 // must be handled otherwise it will segfault. 215#if !FULL_SYSTEM 216 if (squashIt == cpu->instList.begin()) { 217 DPRINTF(ROB, "ROB: Reached head of instruction list while " |
218 "squashing.\n"); 219 |
220 squashIt = cpu->instList.end(); |
221 |
222 doneSquashing = true; |
223 224 return; 225 } |
226#endif |
227 |
228 // Move the tail iterator to the next instruction. 229 squashIt--; |
230 } 231 232 233 // Check if ROB is done squashing. |
234 if ((*squashIt)->seqNum == squashedSeqNum) { 235 DPRINTF(ROB, "ROB: Done squashing instructions.\n"); |
236 |
237 squashIt = cpu->instList.end(); |
238 |
239 doneSquashing = true; |
240 } |
241} 242 |
243template <class Impl> 244void |
245ROB<Impl>::squash(InstSeqNum squash_num) |
246{ |
247 DPRINTF(ROB, "ROB: Starting to squash within the ROB.\n"); 248 doneSquashing = false; |
249 |
250 squashedSeqNum = squash_num; 251 |
252 assert(tail != cpu->instList.end()); |
253 |
254 squashIt = tail; |
255 |
256 doSquash(); |
257} |
258 |
259template <class Impl> 260uint64_t 261ROB<Impl>::readHeadPC() 262{ |
263 assert(numInstsInROB == countInsts()); |
264 |
265 DynInstPtr head_inst = cpu->instList.front(); |
266 267 return head_inst->readPC(); 268} 269 270template <class Impl> 271uint64_t |
272ROB<Impl>::readHeadNextPC() 273{ |
274 assert(numInstsInROB == countInsts()); |
275 |
276 DynInstPtr head_inst = cpu->instList.front(); |
277 278 return head_inst->readNextPC(); 279} 280 281template <class Impl> |
282InstSeqNum 283ROB<Impl>::readHeadSeqNum() 284{ |
285 // Return the last sequence number that has not been squashed. Other 286 // stages can use it to squash any instructions younger than the current 287 // tail. 288 DynInstPtr head_inst = cpu->instList.front(); |
289 290 return head_inst->seqNum; 291} 292 293template <class Impl> |
294uint64_t 295ROB<Impl>::readTailPC() 296{ |
297 assert(numInstsInROB == countInsts()); |
298 |
299 assert(tail != cpu->instList.end()); |
300 301 return (*tail)->readPC(); 302} 303 304template <class Impl> |
305InstSeqNum 306ROB<Impl>::readTailSeqNum() 307{ 308 // Return the last sequence number that has not been squashed. Other 309 // stages can use it to squash any instructions younger than the current 310 // tail. 311 return (*tail)->seqNum; 312} 313 |
314#endif // __CPU_O3_CPU_ROB_IMPL_HH__ |