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> * Copyright (c) 2012 ARM Limited
> * All rights reserved
> *
> * The license below extends only to copyright in the software and shall
> * not be construed as granting a license to any other intellectual
> * property including but not limited to intellectual property relating
> * to a hardware implementation of the functionality of the software
> * licensed hereunder. You may use the software subject to the license
> * terms below provided that you ensure that this notice is replicated
> * unmodified and in its entirety in all distributions of the software,
> * modified or unmodified, in source code or in binary form.
> *
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< for (ThreadID tid = 0; tid < numThreads; tid++) {
< squashedSeqNum[tid] = 0;
< doneSquashing[tid] = true;
< threadEntries[tid] = 0;
< }
<
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< // Set the per-thread iterators to the end of the instruction list.
< for (ThreadID tid = 0; tid < numThreads; tid++) {
---
> resetState();
> }
>
> template <class Impl>
> void
> ROB<Impl>::resetState()
> {
> for (ThreadID tid = 0; tid < numThreads; tid++) {
> doneSquashing[tid] = true;
> threadEntries[tid] = 0;
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> squashedSeqNum[tid] = 0;
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> numInstsInROB = 0;
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< ROB<Impl>::switchOut()
---
> ROB<Impl>::drainSanityCheck() const
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< for (ThreadID tid = 0; tid < numThreads; tid++) {
< instList[tid].clear();
< }
---
> for (ThreadID tid = 0; tid < numThreads; tid++)
> assert(instList[tid].empty());
> assert(isEmpty());
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< for (ThreadID tid = 0; tid < numThreads; tid++) {
< doneSquashing[tid] = true;
< threadEntries[tid] = 0;
< squashIt[tid] = instList[tid].end();
< }
< numInstsInROB = 0;
<
< // Initialize the "universal" ROB head & tail point to invalid
< // pointers
< head = instList[0].end();
< tail = instList[0].end();
---
> resetState();