rob.hh (2632:1bb2f91485ea) rob.hh (2654:9559cfa91b9d)
1/*
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the

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21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the

--- 10 unchanged lines hidden (view full) ---

21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29// Todo: Probably add in support for scheduling events (more than one as
30// well) on the case of the ROB being empty or full. Considering tracking
31// free entries instead of insts in ROB. Differentiate between squashing
32// all instructions after the instruction, and all instructions after *and*
33// including that instruction.
29#ifndef __CPU_O3_ROB_HH__
30#define __CPU_O3_ROB_HH__
34
31
35#ifndef __CPU_O3_CPU_ROB_HH__
36#define __CPU_O3_CPU_ROB_HH__
37
32#include <string>
38#include <utility>
39#include <vector>
40
41/**
33#include <utility>
34#include <vector>
35
36/**
42 * ROB class. Uses the instruction list that exists within the CPU to
43 * represent the ROB. This class doesn't contain that list, but instead
44 * a pointer to the CPU to get access to the list. The ROB, in this first
45 * implementation, is largely what drives squashing.
37 * ROB class. The ROB is largely what drives squashing.
46 */
47template <class Impl>
48class ROB
49{
50 protected:
51 typedef TheISA::RegIndex RegIndex;
52 public:
53 //Typedefs from the Impl.
54 typedef typename Impl::FullCPU FullCPU;
55 typedef typename Impl::DynInstPtr DynInstPtr;
56
38 */
39template <class Impl>
40class ROB
41{
42 protected:
43 typedef TheISA::RegIndex RegIndex;
44 public:
45 //Typedefs from the Impl.
46 typedef typename Impl::FullCPU FullCPU;
47 typedef typename Impl::DynInstPtr DynInstPtr;
48
57 typedef std::pair<RegIndex, PhysRegIndex> UnmapInfo_t;
58 typedef typename list<DynInstPtr>::iterator InstIt_t;
49 typedef std::pair UnmapInfo;
50 typedef typename std::list<DynInstPtr>::iterator InstIt;
59
51
52 /** Possible ROB statuses. */
53 enum Status {
54 Running,
55 Idle,
56 ROBSquashing
57 };
58
59 /** SMT ROB Sharing Policy */
60 enum ROBPolicy{
61 Dynamic,
62 Partitioned,
63 Threshold
64 };
65
66 private:
67 /** Per-thread ROB status. */
68 Status robStatus[Impl::MaxThreads];
69
70 /** ROB resource sharing policy for SMT mode. */
71 ROBPolicy robPolicy;
72
60 public:
61 /** ROB constructor.
73 public:
74 /** ROB constructor.
62 * @param _numEntries Number of entries in ROB.
63 * @param _squashWidth Number of instructions that can be squashed in a
64 * single cycle.
75 * @param _numEntries Number of entries in ROB.
76 * @param _squashWidth Number of instructions that can be squashed in a
77 * single cycle.
78 * @param _smtROBPolicy ROB Partitioning Scheme for SMT.
79 * @param _smtROBThreshold Max Resources(by %) a thread can have in the ROB.
80 * @param _numThreads The number of active threads.
65 */
81 */
66 ROB(unsigned _numEntries, unsigned _squashWidth);
82 ROB(unsigned _numEntries, unsigned _squashWidth, std::string smtROBPolicy,
83 unsigned _smtROBThreshold, unsigned _numThreads);
67
84
85 std::string name() const;
86
68 /** Function to set the CPU pointer, necessary due to which object the ROB
69 * is created within.
70 * @param cpu_ptr Pointer to the implementation specific full CPU object.
71 */
72 void setCPU(FullCPU *cpu_ptr);
73
87 /** Function to set the CPU pointer, necessary due to which object the ROB
88 * is created within.
89 * @param cpu_ptr Pointer to the implementation specific full CPU object.
90 */
91 void setCPU(FullCPU *cpu_ptr);
92
74 /** Function to insert an instruction into the ROB. The parameter inst is
75 * not truly required, but is useful for checking correctness. Note
76 * that whatever calls this function must ensure that there is enough
77 * space within the ROB for the new instruction.
93 /** Sets pointer to the list of active threads.
94 * @param at_ptr Pointer to the list of active threads.
95 */
96 void setActiveThreads(std::list<unsigned>* at_ptr);
97
98 void switchOut();
99
100 void takeOverFrom();
101
102 /** Function to insert an instruction into the ROB. Note that whatever
103 * calls this function must ensure that there is enough space within the
104 * ROB for the new instruction.
78 * @param inst The instruction being inserted into the ROB.
105 * @param inst The instruction being inserted into the ROB.
79 * @todo Remove the parameter once correctness is ensured.
80 */
81 void insertInst(DynInstPtr &inst);
82
83 /** Returns pointer to the head instruction within the ROB. There is
84 * no guarantee as to the return value if the ROB is empty.
85 * @retval Pointer to the DynInst that is at the head of the ROB.
86 */
106 */
107 void insertInst(DynInstPtr &inst);
108
109 /** Returns pointer to the head instruction within the ROB. There is
110 * no guarantee as to the return value if the ROB is empty.
111 * @retval Pointer to the DynInst that is at the head of the ROB.
112 */
87 DynInstPtr readHeadInst() { return cpu->instList.front(); }
113// DynInstPtr readHeadInst();
88
114
89 DynInstPtr readTailInst() { return (*tail); }
115 /** Returns a pointer to the head instruction of a specific thread within
116 * the ROB.
117 * @return Pointer to the DynInst that is at the head of the ROB.
118 */
119 DynInstPtr readHeadInst(unsigned tid);
90
120
91 void retireHead();
121 /** Returns pointer to the tail instruction within the ROB. There is
122 * no guarantee as to the return value if the ROB is empty.
123 * @retval Pointer to the DynInst that is at the tail of the ROB.
124 */
125// DynInstPtr readTailInst();
92
126
93 bool isHeadReady();
127 /** Returns a pointer to the tail instruction of a specific thread within
128 * the ROB.
129 * @return Pointer to the DynInst that is at the tail of the ROB.
130 */
131 DynInstPtr readTailInst(unsigned tid);
94
132
133 /** Retires the head instruction, removing it from the ROB. */
134// void retireHead();
135
136 /** Retires the head instruction of a specific thread, removing it from the
137 * ROB.
138 */
139 void retireHead(unsigned tid);
140
141 /** Is the oldest instruction across all threads ready. */
142// bool isHeadReady();
143
144 /** Is the oldest instruction across a particular thread ready. */
145 bool isHeadReady(unsigned tid);
146
147 /** Is there any commitable head instruction across all threads ready. */
148 bool canCommit();
149
150 /** Re-adjust ROB partitioning. */
151 void resetEntries();
152
153 /** Number of entries needed For 'num_threads' amount of threads. */
154 int entryAmount(int num_threads);
155
156 /** Returns the number of total free entries in the ROB. */
95 unsigned numFreeEntries();
96
157 unsigned numFreeEntries();
158
159 /** Returns the number of free entries in a specific ROB paritition. */
160 unsigned numFreeEntries(unsigned tid);
161
162 /** Returns the maximum number of entries for a specific thread. */
163 unsigned getMaxEntries(unsigned tid)
164 { return maxEntries[tid]; }
165
166 /** Returns the number of entries being used by a specific thread. */
167 unsigned getThreadEntries(unsigned tid)
168 { return threadEntries[tid]; }
169
170 /** Returns if the ROB is full. */
97 bool isFull()
98 { return numInstsInROB == numEntries; }
99
171 bool isFull()
172 { return numInstsInROB == numEntries; }
173
174 /** Returns if a specific thread's partition is full. */
175 bool isFull(unsigned tid)
176 { return threadEntries[tid] == numEntries; }
177
178 /** Returns if the ROB is empty. */
100 bool isEmpty()
101 { return numInstsInROB == 0; }
102
179 bool isEmpty()
180 { return numInstsInROB == 0; }
181
103 void doSquash();
182 /** Returns if a specific thread's partition is empty. */
183 bool isEmpty(unsigned tid)
184 { return threadEntries[tid] == 0; }
104
185
105 void squash(InstSeqNum squash_num);
186 /** Executes the squash, marking squashed instructions. */
187 void doSquash(unsigned tid);
106
188
107 uint64_t readHeadPC();
189 /** Squashes all instructions younger than the given sequence number for
190 * the specific thread.
191 */
192 void squash(InstSeqNum squash_num, unsigned tid);
108
193
109 uint64_t readHeadNextPC();
194 /** Updates the head instruction with the new oldest instruction. */
195 void updateHead();
110
196
111 InstSeqNum readHeadSeqNum();
197 /** Updates the tail instruction with the new youngest instruction. */
198 void updateTail();
112
199
113 uint64_t readTailPC();
200 /** Reads the PC of the oldest head instruction. */
201// uint64_t readHeadPC();
114
202
115 InstSeqNum readTailSeqNum();
203 /** Reads the PC of the head instruction of a specific thread. */
204// uint64_t readHeadPC(unsigned tid);
116
205
206 /** Reads the next PC of the oldest head instruction. */
207// uint64_t readHeadNextPC();
208
209 /** Reads the next PC of the head instruction of a specific thread. */
210// uint64_t readHeadNextPC(unsigned tid);
211
212 /** Reads the sequence number of the oldest head instruction. */
213// InstSeqNum readHeadSeqNum();
214
215 /** Reads the sequence number of the head instruction of a specific thread.
216 */
217// InstSeqNum readHeadSeqNum(unsigned tid);
218
219 /** Reads the PC of the youngest tail instruction. */
220// uint64_t readTailPC();
221
222 /** Reads the PC of the tail instruction of a specific thread. */
223// uint64_t readTailPC(unsigned tid);
224
225 /** Reads the sequence number of the youngest tail instruction. */
226// InstSeqNum readTailSeqNum();
227
228 /** Reads the sequence number of tail instruction of a specific thread. */
229// InstSeqNum readTailSeqNum(unsigned tid);
230
117 /** Checks if the ROB is still in the process of squashing instructions.
118 * @retval Whether or not the ROB is done squashing.
119 */
231 /** Checks if the ROB is still in the process of squashing instructions.
232 * @retval Whether or not the ROB is done squashing.
233 */
120 bool isDoneSquashing() const { return doneSquashing; }
234 bool isDoneSquashing(unsigned tid) const
235 { return doneSquashing[tid]; }
121
236
237 /** Checks if the ROB is still in the process of squashing instructions for
238 * any thread.
239 */
240 bool isDoneSquashing();
241
122 /** This is more of a debugging function than anything. Use
123 * numInstsInROB to get the instructions in the ROB unless you are
124 * double checking that variable.
125 */
126 int countInsts();
127
242 /** This is more of a debugging function than anything. Use
243 * numInstsInROB to get the instructions in the ROB unless you are
244 * double checking that variable.
245 */
246 int countInsts();
247
128 private:
248 /** This is more of a debugging function than anything. Use
249 * threadEntries to get the instructions in the ROB unless you are
250 * double checking that variable.
251 */
252 int countInsts(unsigned tid);
129
253
254 private:
130 /** Pointer to the CPU. */
131 FullCPU *cpu;
132
255 /** Pointer to the CPU. */
256 FullCPU *cpu;
257
258 /** Active Threads in CPU */
259 std::list<unsigned>* activeThreads;
260
133 /** Number of instructions in the ROB. */
134 unsigned numEntries;
135
261 /** Number of instructions in the ROB. */
262 unsigned numEntries;
263
264 /** Entries Per Thread */
265 unsigned threadEntries[Impl::MaxThreads];
266
267 /** Max Insts a Thread Can Have in the ROB */
268 unsigned maxEntries[Impl::MaxThreads];
269
270 /** ROB List of Instructions */
271 std::list<DynInstPtr> instList[Impl::MaxThreads];
272
136 /** Number of instructions that can be squashed in a single cycle. */
137 unsigned squashWidth;
138
273 /** Number of instructions that can be squashed in a single cycle. */
274 unsigned squashWidth;
275
276 public:
139 /** Iterator pointing to the instruction which is the last instruction
140 * in the ROB. This may at times be invalid (ie when the ROB is empty),
141 * however it should never be incorrect.
142 */
277 /** Iterator pointing to the instruction which is the last instruction
278 * in the ROB. This may at times be invalid (ie when the ROB is empty),
279 * however it should never be incorrect.
280 */
143 InstIt_t tail;
281 InstIt tail;
144
282
283 /** Iterator pointing to the instruction which is the first instruction in
284 * in the ROB*/
285 InstIt head;
286
287 private:
145 /** Iterator used for walking through the list of instructions when
146 * squashing. Used so that there is persistent state between cycles;
147 * when squashing, the instructions are marked as squashed but not
148 * immediately removed, meaning the tail iterator remains the same before
149 * and after a squash.
150 * This will always be set to cpu->instList.end() if it is invalid.
151 */
288 /** Iterator used for walking through the list of instructions when
289 * squashing. Used so that there is persistent state between cycles;
290 * when squashing, the instructions are marked as squashed but not
291 * immediately removed, meaning the tail iterator remains the same before
292 * and after a squash.
293 * This will always be set to cpu->instList.end() if it is invalid.
294 */
152 InstIt_t squashIt;
295 InstIt squashIt[Impl::MaxThreads];
153
296
297 public:
154 /** Number of instructions in the ROB. */
155 int numInstsInROB;
156
298 /** Number of instructions in the ROB. */
299 int numInstsInROB;
300
301 DynInstPtr dummyInst;
302
303 private:
157 /** The sequence number of the squashed instruction. */
158 InstSeqNum squashedSeqNum;
159
160 /** Is the ROB done squashing. */
304 /** The sequence number of the squashed instruction. */
305 InstSeqNum squashedSeqNum;
306
307 /** Is the ROB done squashing. */
161 bool doneSquashing;
308 bool doneSquashing[Impl::MaxThreads];
309
310 /** Number of active threads. */
311 unsigned numThreads;
162};
163
312};
313
164#endif //__CPU_O3_CPU_ROB_HH__
314#endif //__CPU_O3_ROB_HH__