1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 * Korey Sewell
42 */
43
44#ifndef __CPU_O3_ROB_HH__
45#define __CPU_O3_ROB_HH__
46
47#include <string>
48#include <utility>
49#include <vector>
50
51#include "arch/registers.hh"
52#include "base/types.hh"
53#include "config/the_isa.hh"
54
55struct DerivO3CPUParams;
56
57/**
58 * ROB class. The ROB is largely what drives squashing.
59 */
60template <class Impl>
61class ROB
62{
63 public:
64 //Typedefs from the Impl.
65 typedef typename Impl::O3CPU O3CPU;
66 typedef typename Impl::DynInstPtr DynInstPtr;
67
68 typedef std::pair<RegIndex, PhysRegIndex> UnmapInfo;
69 typedef typename std::list<DynInstPtr>::iterator InstIt;
70
71 /** Possible ROB statuses. */
72 enum Status {
73 Running,
74 Idle,
75 ROBSquashing
76 };
77
78 /** SMT ROB Sharing Policy */
79 enum ROBPolicy{
80 Dynamic,
81 Partitioned,
82 Threshold
83 };
84
85 private:
86 /** Per-thread ROB status. */
87 Status robStatus[Impl::MaxThreads];
88
89 /** ROB resource sharing policy for SMT mode. */
90 ROBPolicy robPolicy;
91
92 public:
93 /** ROB constructor.
94 * @param _cpu The cpu object pointer.
95 * @param params The cpu params including several ROB-specific parameters.
96 */
97 ROB(O3CPU *_cpu, DerivO3CPUParams *params);
98
99 std::string name() const;
100
101 /** Sets pointer to the list of active threads.
102 * @param at_ptr Pointer to the list of active threads.
103 */
104 void setActiveThreads(std::list<ThreadID> *at_ptr);
105
106 /** Perform sanity checks after a drain. */
107 void drainSanityCheck() const;
108
109 /** Takes over another CPU's thread. */
110 void takeOverFrom();
111
112 /** Function to insert an instruction into the ROB. Note that whatever
113 * calls this function must ensure that there is enough space within the
114 * ROB for the new instruction.
115 * @param inst The instruction being inserted into the ROB.
116 */
| 1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 * Korey Sewell
42 */
43
44#ifndef __CPU_O3_ROB_HH__
45#define __CPU_O3_ROB_HH__
46
47#include <string>
48#include <utility>
49#include <vector>
50
51#include "arch/registers.hh"
52#include "base/types.hh"
53#include "config/the_isa.hh"
54
55struct DerivO3CPUParams;
56
57/**
58 * ROB class. The ROB is largely what drives squashing.
59 */
60template <class Impl>
61class ROB
62{
63 public:
64 //Typedefs from the Impl.
65 typedef typename Impl::O3CPU O3CPU;
66 typedef typename Impl::DynInstPtr DynInstPtr;
67
68 typedef std::pair<RegIndex, PhysRegIndex> UnmapInfo;
69 typedef typename std::list<DynInstPtr>::iterator InstIt;
70
71 /** Possible ROB statuses. */
72 enum Status {
73 Running,
74 Idle,
75 ROBSquashing
76 };
77
78 /** SMT ROB Sharing Policy */
79 enum ROBPolicy{
80 Dynamic,
81 Partitioned,
82 Threshold
83 };
84
85 private:
86 /** Per-thread ROB status. */
87 Status robStatus[Impl::MaxThreads];
88
89 /** ROB resource sharing policy for SMT mode. */
90 ROBPolicy robPolicy;
91
92 public:
93 /** ROB constructor.
94 * @param _cpu The cpu object pointer.
95 * @param params The cpu params including several ROB-specific parameters.
96 */
97 ROB(O3CPU *_cpu, DerivO3CPUParams *params);
98
99 std::string name() const;
100
101 /** Sets pointer to the list of active threads.
102 * @param at_ptr Pointer to the list of active threads.
103 */
104 void setActiveThreads(std::list<ThreadID> *at_ptr);
105
106 /** Perform sanity checks after a drain. */
107 void drainSanityCheck() const;
108
109 /** Takes over another CPU's thread. */
110 void takeOverFrom();
111
112 /** Function to insert an instruction into the ROB. Note that whatever
113 * calls this function must ensure that there is enough space within the
114 * ROB for the new instruction.
115 * @param inst The instruction being inserted into the ROB.
116 */
|
130
131 /** Returns a pointer to the instruction with the given sequence if it is
132 * in the ROB.
133 */
134 DynInstPtr findInst(ThreadID tid, InstSeqNum squash_inst);
135
136 /** Returns pointer to the tail instruction within the ROB. There is
137 * no guarantee as to the return value if the ROB is empty.
138 * @retval Pointer to the DynInst that is at the tail of the ROB.
139 */
140// DynInstPtr readTailInst();
141
142 /** Returns a pointer to the tail instruction of a specific thread within
143 * the ROB.
144 * @return Pointer to the DynInst that is at the tail of the ROB.
145 */
146 DynInstPtr readTailInst(ThreadID tid);
147
148 /** Retires the head instruction, removing it from the ROB. */
149// void retireHead();
150
151 /** Retires the head instruction of a specific thread, removing it from the
152 * ROB.
153 */
154 void retireHead(ThreadID tid);
155
156 /** Is the oldest instruction across all threads ready. */
157// bool isHeadReady();
158
159 /** Is the oldest instruction across a particular thread ready. */
160 bool isHeadReady(ThreadID tid);
161
162 /** Is there any commitable head instruction across all threads ready. */
163 bool canCommit();
164
165 /** Re-adjust ROB partitioning. */
166 void resetEntries();
167
168 /** Number of entries needed For 'num_threads' amount of threads. */
169 int entryAmount(ThreadID num_threads);
170
171 /** Returns the number of total free entries in the ROB. */
172 unsigned numFreeEntries();
173
174 /** Returns the number of free entries in a specific ROB paritition. */
175 unsigned numFreeEntries(ThreadID tid);
176
177 /** Returns the maximum number of entries for a specific thread. */
178 unsigned getMaxEntries(ThreadID tid)
179 { return maxEntries[tid]; }
180
181 /** Returns the number of entries being used by a specific thread. */
182 unsigned getThreadEntries(ThreadID tid)
183 { return threadEntries[tid]; }
184
185 /** Returns if the ROB is full. */
186 bool isFull()
187 { return numInstsInROB == numEntries; }
188
189 /** Returns if a specific thread's partition is full. */
190 bool isFull(ThreadID tid)
191 { return threadEntries[tid] == numEntries; }
192
193 /** Returns if the ROB is empty. */
194 bool isEmpty() const
195 { return numInstsInROB == 0; }
196
197 /** Returns if a specific thread's partition is empty. */
198 bool isEmpty(ThreadID tid) const
199 { return threadEntries[tid] == 0; }
200
201 /** Executes the squash, marking squashed instructions. */
202 void doSquash(ThreadID tid);
203
204 /** Squashes all instructions younger than the given sequence number for
205 * the specific thread.
206 */
207 void squash(InstSeqNum squash_num, ThreadID tid);
208
209 /** Updates the head instruction with the new oldest instruction. */
210 void updateHead();
211
212 /** Updates the tail instruction with the new youngest instruction. */
213 void updateTail();
214
215 /** Reads the PC of the oldest head instruction. */
216// uint64_t readHeadPC();
217
218 /** Reads the PC of the head instruction of a specific thread. */
219// uint64_t readHeadPC(ThreadID tid);
220
221 /** Reads the next PC of the oldest head instruction. */
222// uint64_t readHeadNextPC();
223
224 /** Reads the next PC of the head instruction of a specific thread. */
225// uint64_t readHeadNextPC(ThreadID tid);
226
227 /** Reads the sequence number of the oldest head instruction. */
228// InstSeqNum readHeadSeqNum();
229
230 /** Reads the sequence number of the head instruction of a specific thread.
231 */
232// InstSeqNum readHeadSeqNum(ThreadID tid);
233
234 /** Reads the PC of the youngest tail instruction. */
235// uint64_t readTailPC();
236
237 /** Reads the PC of the tail instruction of a specific thread. */
238// uint64_t readTailPC(ThreadID tid);
239
240 /** Reads the sequence number of the youngest tail instruction. */
241// InstSeqNum readTailSeqNum();
242
243 /** Reads the sequence number of tail instruction of a specific thread. */
244// InstSeqNum readTailSeqNum(ThreadID tid);
245
246 /** Checks if the ROB is still in the process of squashing instructions.
247 * @retval Whether or not the ROB is done squashing.
248 */
249 bool isDoneSquashing(ThreadID tid) const
250 { return doneSquashing[tid]; }
251
252 /** Checks if the ROB is still in the process of squashing instructions for
253 * any thread.
254 */
255 bool isDoneSquashing();
256
257 /** This is more of a debugging function than anything. Use
258 * numInstsInROB to get the instructions in the ROB unless you are
259 * double checking that variable.
260 */
261 int countInsts();
262
263 /** This is more of a debugging function than anything. Use
264 * threadEntries to get the instructions in the ROB unless you are
265 * double checking that variable.
266 */
267 int countInsts(ThreadID tid);
268
269 /** Registers statistics. */
270 void regStats();
271
272 private:
273 /** Reset the ROB state */
274 void resetState();
275
276 /** Pointer to the CPU. */
277 O3CPU *cpu;
278
279 /** Active Threads in CPU */
280 std::list<ThreadID> *activeThreads;
281
282 /** Number of instructions in the ROB. */
283 unsigned numEntries;
284
285 /** Entries Per Thread */
286 unsigned threadEntries[Impl::MaxThreads];
287
288 /** Max Insts a Thread Can Have in the ROB */
289 unsigned maxEntries[Impl::MaxThreads];
290
291 /** ROB List of Instructions */
292 std::list<DynInstPtr> instList[Impl::MaxThreads];
293
294 /** Number of instructions that can be squashed in a single cycle. */
295 unsigned squashWidth;
296
297 public:
298 /** Iterator pointing to the instruction which is the last instruction
299 * in the ROB. This may at times be invalid (ie when the ROB is empty),
300 * however it should never be incorrect.
301 */
302 InstIt tail;
303
304 /** Iterator pointing to the instruction which is the first instruction in
305 * in the ROB*/
306 InstIt head;
307
308 private:
309 /** Iterator used for walking through the list of instructions when
310 * squashing. Used so that there is persistent state between cycles;
311 * when squashing, the instructions are marked as squashed but not
312 * immediately removed, meaning the tail iterator remains the same before
313 * and after a squash.
314 * This will always be set to cpu->instList.end() if it is invalid.
315 */
316 InstIt squashIt[Impl::MaxThreads];
317
318 public:
319 /** Number of instructions in the ROB. */
320 int numInstsInROB;
321
322 /** Dummy instruction returned if there are no insts left. */
323 DynInstPtr dummyInst;
324
325 private:
326 /** The sequence number of the squashed instruction. */
327 InstSeqNum squashedSeqNum[Impl::MaxThreads];
328
329 /** Is the ROB done squashing. */
330 bool doneSquashing[Impl::MaxThreads];
331
332 /** Number of active threads. */
333 ThreadID numThreads;
334
335 // The number of rob_reads
336 Stats::Scalar robReads;
337 // The number of rob_writes
338 Stats::Scalar robWrites;
339};
340
341#endif //__CPU_O3_ROB_HH__
| 130
131 /** Returns a pointer to the instruction with the given sequence if it is
132 * in the ROB.
133 */
134 DynInstPtr findInst(ThreadID tid, InstSeqNum squash_inst);
135
136 /** Returns pointer to the tail instruction within the ROB. There is
137 * no guarantee as to the return value if the ROB is empty.
138 * @retval Pointer to the DynInst that is at the tail of the ROB.
139 */
140// DynInstPtr readTailInst();
141
142 /** Returns a pointer to the tail instruction of a specific thread within
143 * the ROB.
144 * @return Pointer to the DynInst that is at the tail of the ROB.
145 */
146 DynInstPtr readTailInst(ThreadID tid);
147
148 /** Retires the head instruction, removing it from the ROB. */
149// void retireHead();
150
151 /** Retires the head instruction of a specific thread, removing it from the
152 * ROB.
153 */
154 void retireHead(ThreadID tid);
155
156 /** Is the oldest instruction across all threads ready. */
157// bool isHeadReady();
158
159 /** Is the oldest instruction across a particular thread ready. */
160 bool isHeadReady(ThreadID tid);
161
162 /** Is there any commitable head instruction across all threads ready. */
163 bool canCommit();
164
165 /** Re-adjust ROB partitioning. */
166 void resetEntries();
167
168 /** Number of entries needed For 'num_threads' amount of threads. */
169 int entryAmount(ThreadID num_threads);
170
171 /** Returns the number of total free entries in the ROB. */
172 unsigned numFreeEntries();
173
174 /** Returns the number of free entries in a specific ROB paritition. */
175 unsigned numFreeEntries(ThreadID tid);
176
177 /** Returns the maximum number of entries for a specific thread. */
178 unsigned getMaxEntries(ThreadID tid)
179 { return maxEntries[tid]; }
180
181 /** Returns the number of entries being used by a specific thread. */
182 unsigned getThreadEntries(ThreadID tid)
183 { return threadEntries[tid]; }
184
185 /** Returns if the ROB is full. */
186 bool isFull()
187 { return numInstsInROB == numEntries; }
188
189 /** Returns if a specific thread's partition is full. */
190 bool isFull(ThreadID tid)
191 { return threadEntries[tid] == numEntries; }
192
193 /** Returns if the ROB is empty. */
194 bool isEmpty() const
195 { return numInstsInROB == 0; }
196
197 /** Returns if a specific thread's partition is empty. */
198 bool isEmpty(ThreadID tid) const
199 { return threadEntries[tid] == 0; }
200
201 /** Executes the squash, marking squashed instructions. */
202 void doSquash(ThreadID tid);
203
204 /** Squashes all instructions younger than the given sequence number for
205 * the specific thread.
206 */
207 void squash(InstSeqNum squash_num, ThreadID tid);
208
209 /** Updates the head instruction with the new oldest instruction. */
210 void updateHead();
211
212 /** Updates the tail instruction with the new youngest instruction. */
213 void updateTail();
214
215 /** Reads the PC of the oldest head instruction. */
216// uint64_t readHeadPC();
217
218 /** Reads the PC of the head instruction of a specific thread. */
219// uint64_t readHeadPC(ThreadID tid);
220
221 /** Reads the next PC of the oldest head instruction. */
222// uint64_t readHeadNextPC();
223
224 /** Reads the next PC of the head instruction of a specific thread. */
225// uint64_t readHeadNextPC(ThreadID tid);
226
227 /** Reads the sequence number of the oldest head instruction. */
228// InstSeqNum readHeadSeqNum();
229
230 /** Reads the sequence number of the head instruction of a specific thread.
231 */
232// InstSeqNum readHeadSeqNum(ThreadID tid);
233
234 /** Reads the PC of the youngest tail instruction. */
235// uint64_t readTailPC();
236
237 /** Reads the PC of the tail instruction of a specific thread. */
238// uint64_t readTailPC(ThreadID tid);
239
240 /** Reads the sequence number of the youngest tail instruction. */
241// InstSeqNum readTailSeqNum();
242
243 /** Reads the sequence number of tail instruction of a specific thread. */
244// InstSeqNum readTailSeqNum(ThreadID tid);
245
246 /** Checks if the ROB is still in the process of squashing instructions.
247 * @retval Whether or not the ROB is done squashing.
248 */
249 bool isDoneSquashing(ThreadID tid) const
250 { return doneSquashing[tid]; }
251
252 /** Checks if the ROB is still in the process of squashing instructions for
253 * any thread.
254 */
255 bool isDoneSquashing();
256
257 /** This is more of a debugging function than anything. Use
258 * numInstsInROB to get the instructions in the ROB unless you are
259 * double checking that variable.
260 */
261 int countInsts();
262
263 /** This is more of a debugging function than anything. Use
264 * threadEntries to get the instructions in the ROB unless you are
265 * double checking that variable.
266 */
267 int countInsts(ThreadID tid);
268
269 /** Registers statistics. */
270 void regStats();
271
272 private:
273 /** Reset the ROB state */
274 void resetState();
275
276 /** Pointer to the CPU. */
277 O3CPU *cpu;
278
279 /** Active Threads in CPU */
280 std::list<ThreadID> *activeThreads;
281
282 /** Number of instructions in the ROB. */
283 unsigned numEntries;
284
285 /** Entries Per Thread */
286 unsigned threadEntries[Impl::MaxThreads];
287
288 /** Max Insts a Thread Can Have in the ROB */
289 unsigned maxEntries[Impl::MaxThreads];
290
291 /** ROB List of Instructions */
292 std::list<DynInstPtr> instList[Impl::MaxThreads];
293
294 /** Number of instructions that can be squashed in a single cycle. */
295 unsigned squashWidth;
296
297 public:
298 /** Iterator pointing to the instruction which is the last instruction
299 * in the ROB. This may at times be invalid (ie when the ROB is empty),
300 * however it should never be incorrect.
301 */
302 InstIt tail;
303
304 /** Iterator pointing to the instruction which is the first instruction in
305 * in the ROB*/
306 InstIt head;
307
308 private:
309 /** Iterator used for walking through the list of instructions when
310 * squashing. Used so that there is persistent state between cycles;
311 * when squashing, the instructions are marked as squashed but not
312 * immediately removed, meaning the tail iterator remains the same before
313 * and after a squash.
314 * This will always be set to cpu->instList.end() if it is invalid.
315 */
316 InstIt squashIt[Impl::MaxThreads];
317
318 public:
319 /** Number of instructions in the ROB. */
320 int numInstsInROB;
321
322 /** Dummy instruction returned if there are no insts left. */
323 DynInstPtr dummyInst;
324
325 private:
326 /** The sequence number of the squashed instruction. */
327 InstSeqNum squashedSeqNum[Impl::MaxThreads];
328
329 /** Is the ROB done squashing. */
330 bool doneSquashing[Impl::MaxThreads];
331
332 /** Number of active threads. */
333 ThreadID numThreads;
334
335 // The number of rob_reads
336 Stats::Scalar robReads;
337 // The number of rob_writes
338 Stats::Scalar robWrites;
339};
340
341#endif //__CPU_O3_ROB_HH__
|