1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the

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19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31// Todo: Probably add in support for scheduling events (more than one as
32// well) on the case of the ROB being empty or full. Considering tracking
33// free entries instead of insts in ROB. Differentiate between squashing
34// all instructions after the instruction, and all instructions after *and*
35// including that instruction.
36
37#ifndef __CPU_O3_CPU_ROB_HH__
38#define __CPU_O3_CPU_ROB_HH__
39
40#include <utility>
41#include <vector>
42
43/**
44 * ROB class. Uses the instruction list that exists within the CPU to
45 * represent the ROB. This class doesn't contain that list, but instead
46 * a pointer to the CPU to get access to the list. The ROB, in this first
47 * implementation, is largely what drives squashing.
48 */
49template <class Impl>
50class ROB
51{
52 protected:
53 typedef TheISA::RegIndex RegIndex;
54 public:
55 //Typedefs from the Impl.
56 typedef typename Impl::FullCPU FullCPU;
57 typedef typename Impl::DynInstPtr DynInstPtr;
58
59 typedef std::pair<RegIndex, PhysRegIndex> UnmapInfo_t;
60 typedef typename list<DynInstPtr>::iterator InstIt_t;
61
62 public:
63 /** ROB constructor.
64 * @param _numEntries Number of entries in ROB.
65 * @param _squashWidth Number of instructions that can be squashed in a
66 * single cycle.
67 */
68 ROB(unsigned _numEntries, unsigned _squashWidth);
69
70 /** Function to set the CPU pointer, necessary due to which object the ROB
71 * is created within.
72 * @param cpu_ptr Pointer to the implementation specific full CPU object.
73 */
74 void setCPU(FullCPU *cpu_ptr);
75
76 /** Function to insert an instruction into the ROB. The parameter inst is
77 * not truly required, but is useful for checking correctness. Note
78 * that whatever calls this function must ensure that there is enough
79 * space within the ROB for the new instruction.
80 * @param inst The instruction being inserted into the ROB.
81 * @todo Remove the parameter once correctness is ensured.
82 */
83 void insertInst(DynInstPtr &inst);
84
85 /** Returns pointer to the head instruction within the ROB. There is
86 * no guarantee as to the return value if the ROB is empty.
87 * @retval Pointer to the DynInst that is at the head of the ROB.
88 */
89 DynInstPtr readHeadInst() { return cpu->instList.front(); }
90
91 DynInstPtr readTailInst() { return (*tail); }
92
93 void retireHead();
94
95 bool isHeadReady();
96
97 unsigned numFreeEntries();
98
99 bool isFull()
100 { return numInstsInROB == numEntries; }
101
102 bool isEmpty()
103 { return numInstsInROB == 0; }
104
105 void doSquash();
106
107 void squash(InstSeqNum squash_num);
108
109 uint64_t readHeadPC();
110
111 uint64_t readHeadNextPC();
112
113 InstSeqNum readHeadSeqNum();
114
115 uint64_t readTailPC();
116
117 InstSeqNum readTailSeqNum();
118
119 /** Checks if the ROB is still in the process of squashing instructions.
120 * @retval Whether or not the ROB is done squashing.
121 */
122 bool isDoneSquashing() const { return doneSquashing; }
123
124 /** This is more of a debugging function than anything. Use
125 * numInstsInROB to get the instructions in the ROB unless you are
126 * double checking that variable.
127 */
128 int countInsts();
129
130 private:
131
132 /** Pointer to the CPU. */
133 FullCPU *cpu;
134
135 /** Number of instructions in the ROB. */
136 unsigned numEntries;
137
138 /** Number of instructions that can be squashed in a single cycle. */
139 unsigned squashWidth;
140
141 /** Iterator pointing to the instruction which is the last instruction
142 * in the ROB. This may at times be invalid (ie when the ROB is empty),
143 * however it should never be incorrect.
144 */
145 InstIt_t tail;
146
147 /** Iterator used for walking through the list of instructions when
148 * squashing. Used so that there is persistent state between cycles;
149 * when squashing, the instructions are marked as squashed but not
150 * immediately removed, meaning the tail iterator remains the same before
151 * and after a squash.
152 * This will always be set to cpu->instList.end() if it is invalid.
153 */
154 InstIt_t squashIt;
155
156 /** Number of instructions in the ROB. */
157 int numInstsInROB;
158
159 /** The sequence number of the squashed instruction. */
160 InstSeqNum squashedSeqNum;
161
162 /** Is the ROB done squashing. */
163 bool doneSquashing;
164};
165
166#endif //__CPU_O3_CPU_ROB_HH__