rename_map.hh (13601:f5c84915eb7f) | rename_map.hh (13610:5d5404ac6288) |
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1/* | 1/* |
2 * Copyright (c) 2015-2016 ARM Limited | 2 * Copyright (c) 2015-2017 ARM Limited |
3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated --- 156 unchanged lines hidden (view full) --- 167 * while methods that do specify a register class (e.g., renameInt()) 168 * take register indices. 169 */ 170class UnifiedRenameMap 171{ 172 private: 173 static constexpr uint32_t NVecElems = TheISA::NumVecElemPerVecReg; 174 using VecReg = TheISA::VecReg; | 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated --- 156 unchanged lines hidden (view full) --- 167 * while methods that do specify a register class (e.g., renameInt()) 168 * take register indices. 169 */ 170class UnifiedRenameMap 171{ 172 private: 173 static constexpr uint32_t NVecElems = TheISA::NumVecElemPerVecReg; 174 using VecReg = TheISA::VecReg; |
175 using VecPredReg = TheISA::VecPredReg; |
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175 176 /** The integer register rename map */ 177 SimpleRenameMap intMap; 178 179 /** The floating-point register rename map */ 180 SimpleRenameMap floatMap; 181 182 /** The condition-code register rename map */ 183 SimpleRenameMap ccMap; 184 185 /** The vector register rename map */ 186 SimpleRenameMap vecMap; 187 188 /** The vector element register rename map */ 189 SimpleRenameMap vecElemMap; 190 | 176 177 /** The integer register rename map */ 178 SimpleRenameMap intMap; 179 180 /** The floating-point register rename map */ 181 SimpleRenameMap floatMap; 182 183 /** The condition-code register rename map */ 184 SimpleRenameMap ccMap; 185 186 /** The vector register rename map */ 187 SimpleRenameMap vecMap; 188 189 /** The vector element register rename map */ 190 SimpleRenameMap vecElemMap; 191 |
192 /** The predicate register rename map */ 193 SimpleRenameMap predMap; 194 |
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191 using VecMode = Enums::VecRegRenameMode; 192 VecMode vecMode; 193 194 /** 195 * The register file object is used only to get PhysRegIdPtr 196 * on MiscRegs, as they are stored in it. 197 */ 198 PhysRegFile *regFile; --- 31 unchanged lines hidden (view full) --- 230 case FloatRegClass: 231 return floatMap.rename(arch_reg); 232 case VecRegClass: 233 assert(vecMode == Enums::Full); 234 return vecMap.rename(arch_reg); 235 case VecElemClass: 236 assert(vecMode == Enums::Elem); 237 return vecElemMap.rename(arch_reg); | 195 using VecMode = Enums::VecRegRenameMode; 196 VecMode vecMode; 197 198 /** 199 * The register file object is used only to get PhysRegIdPtr 200 * on MiscRegs, as they are stored in it. 201 */ 202 PhysRegFile *regFile; --- 31 unchanged lines hidden (view full) --- 234 case FloatRegClass: 235 return floatMap.rename(arch_reg); 236 case VecRegClass: 237 assert(vecMode == Enums::Full); 238 return vecMap.rename(arch_reg); 239 case VecElemClass: 240 assert(vecMode == Enums::Elem); 241 return vecElemMap.rename(arch_reg); |
242 case VecPredRegClass: 243 return predMap.rename(arch_reg); |
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238 case CCRegClass: 239 return ccMap.rename(arch_reg); 240 case MiscRegClass: 241 { 242 // misc regs aren't really renamed, just remapped 243 PhysRegIdPtr phys_reg = lookup(arch_reg); 244 // Set the new register to the previous one to keep the same 245 // mapping throughout the execution. --- 25 unchanged lines hidden (view full) --- 271 case VecRegClass: 272 assert(vecMode == Enums::Full); 273 return vecMap.lookup(arch_reg); 274 275 case VecElemClass: 276 assert(vecMode == Enums::Elem); 277 return vecElemMap.lookup(arch_reg); 278 | 244 case CCRegClass: 245 return ccMap.rename(arch_reg); 246 case MiscRegClass: 247 { 248 // misc regs aren't really renamed, just remapped 249 PhysRegIdPtr phys_reg = lookup(arch_reg); 250 // Set the new register to the previous one to keep the same 251 // mapping throughout the execution. --- 25 unchanged lines hidden (view full) --- 277 case VecRegClass: 278 assert(vecMode == Enums::Full); 279 return vecMap.lookup(arch_reg); 280 281 case VecElemClass: 282 assert(vecMode == Enums::Elem); 283 return vecElemMap.lookup(arch_reg); 284 |
285 case VecPredRegClass: 286 return predMap.lookup(arch_reg); 287 |
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279 case CCRegClass: 280 return ccMap.lookup(arch_reg); 281 282 case MiscRegClass: 283 // misc regs aren't really renamed, they keep the same 284 // mapping throughout the execution. 285 return regFile->getMiscRegId(arch_reg.flatIndex()); 286 --- 27 unchanged lines hidden (view full) --- 314 assert(vecMode == Enums::Full); 315 return vecMap.setEntry(arch_reg, phys_reg); 316 317 case VecElemClass: 318 assert(phys_reg->isVectorPhysElem()); 319 assert(vecMode == Enums::Elem); 320 return vecElemMap.setEntry(arch_reg, phys_reg); 321 | 288 case CCRegClass: 289 return ccMap.lookup(arch_reg); 290 291 case MiscRegClass: 292 // misc regs aren't really renamed, they keep the same 293 // mapping throughout the execution. 294 return regFile->getMiscRegId(arch_reg.flatIndex()); 295 --- 27 unchanged lines hidden (view full) --- 323 assert(vecMode == Enums::Full); 324 return vecMap.setEntry(arch_reg, phys_reg); 325 326 case VecElemClass: 327 assert(phys_reg->isVectorPhysElem()); 328 assert(vecMode == Enums::Elem); 329 return vecElemMap.setEntry(arch_reg, phys_reg); 330 |
331 case VecPredRegClass: 332 assert(phys_reg->isVecPredPhysReg()); 333 return predMap.setEntry(arch_reg, phys_reg); 334 |
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322 case CCRegClass: 323 assert(phys_reg->isCCPhysReg()); 324 return ccMap.setEntry(arch_reg, phys_reg); 325 326 case MiscRegClass: 327 // Misc registers do not actually rename, so don't change 328 // their mappings. We end up here when a commit or squash 329 // tries to update or undo a hardwired misc reg nmapping, --- 10 unchanged lines hidden (view full) --- 340 /** 341 * Return the minimum number of free entries across all of the 342 * register classes. The minimum is used so we guarantee that 343 * this number of entries is available regardless of which class 344 * of registers is requested. 345 */ 346 unsigned numFreeEntries() const 347 { | 335 case CCRegClass: 336 assert(phys_reg->isCCPhysReg()); 337 return ccMap.setEntry(arch_reg, phys_reg); 338 339 case MiscRegClass: 340 // Misc registers do not actually rename, so don't change 341 // their mappings. We end up here when a commit or squash 342 // tries to update or undo a hardwired misc reg nmapping, --- 10 unchanged lines hidden (view full) --- 353 /** 354 * Return the minimum number of free entries across all of the 355 * register classes. The minimum is used so we guarantee that 356 * this number of entries is available regardless of which class 357 * of registers is requested. 358 */ 359 unsigned numFreeEntries() const 360 { |
348 return std::min( | 361 return std::min(std::min( |
349 std::min(intMap.numFreeEntries(), floatMap.numFreeEntries()), 350 vecMode == Enums::Full ? vecMap.numFreeEntries() | 362 std::min(intMap.numFreeEntries(), floatMap.numFreeEntries()), 363 vecMode == Enums::Full ? vecMap.numFreeEntries() |
351 : vecElemMap.numFreeEntries()); | 364 : vecElemMap.numFreeEntries()), 365 predMap.numFreeEntries()); |
352 } 353 354 unsigned numFreeIntEntries() const { return intMap.numFreeEntries(); } 355 unsigned numFreeFloatEntries() const { return floatMap.numFreeEntries(); } 356 unsigned numFreeVecEntries() const 357 { 358 return vecMode == Enums::Full 359 ? vecMap.numFreeEntries() 360 : vecElemMap.numFreeEntries(); 361 } | 366 } 367 368 unsigned numFreeIntEntries() const { return intMap.numFreeEntries(); } 369 unsigned numFreeFloatEntries() const { return floatMap.numFreeEntries(); } 370 unsigned numFreeVecEntries() const 371 { 372 return vecMode == Enums::Full 373 ? vecMap.numFreeEntries() 374 : vecElemMap.numFreeEntries(); 375 } |
376 unsigned numFreePredEntries() const { return predMap.numFreeEntries(); } |
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362 unsigned numFreeCCEntries() const { return ccMap.numFreeEntries(); } 363 364 /** 365 * Return whether there are enough registers to serve the request. 366 */ 367 bool canRename(uint32_t intRegs, uint32_t floatRegs, uint32_t vectorRegs, | 377 unsigned numFreeCCEntries() const { return ccMap.numFreeEntries(); } 378 379 /** 380 * Return whether there are enough registers to serve the request. 381 */ 382 bool canRename(uint32_t intRegs, uint32_t floatRegs, uint32_t vectorRegs, |
368 uint32_t vecElemRegs, uint32_t ccRegs) const | 383 uint32_t vecElemRegs, uint32_t vecPredRegs, 384 uint32_t ccRegs) const |
369 { 370 return intRegs <= intMap.numFreeEntries() && 371 floatRegs <= floatMap.numFreeEntries() && 372 vectorRegs <= vecMap.numFreeEntries() && 373 vecElemRegs <= vecElemMap.numFreeEntries() && | 385 { 386 return intRegs <= intMap.numFreeEntries() && 387 floatRegs <= floatMap.numFreeEntries() && 388 vectorRegs <= vecMap.numFreeEntries() && 389 vecElemRegs <= vecElemMap.numFreeEntries() && |
390 vecPredRegs <= predMap.numFreeEntries() && |
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374 ccRegs <= ccMap.numFreeEntries(); 375 } 376 /** 377 * Set vector mode to Full or Elem. 378 * Ignore 'silent' modifications. 379 * 380 * @param newVecMode new vector renaming mode 381 */ 382 void switchMode(VecMode newVecMode); 383 384 /** 385 * Switch freeList of registers from Full to Elem or vicevers 386 * depending on vecMode (vector renaming mode). 387 */ 388 void switchFreeList(UnifiedFreeList* freeList); 389 390}; 391 392#endif //__CPU_O3_RENAME_MAP_HH__ | 391 ccRegs <= ccMap.numFreeEntries(); 392 } 393 /** 394 * Set vector mode to Full or Elem. 395 * Ignore 'silent' modifications. 396 * 397 * @param newVecMode new vector renaming mode 398 */ 399 void switchMode(VecMode newVecMode); 400 401 /** 402 * Switch freeList of registers from Full to Elem or vicevers 403 * depending on vecMode (vector renaming mode). 404 */ 405 void switchFreeList(UnifiedFreeList* freeList); 406 407}; 408 409#endif //__CPU_O3_RENAME_MAP_HH__ |