rename_map.hh (12106:7784fac1b159) rename_map.hh (12109:f29e9c5418aa)
1/*
2 * Copyright (c) 2015-2016 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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49#include <utility>
50#include <vector>
51
52#include "arch/types.hh"
53#include "config/the_isa.hh"
54#include "cpu/o3/free_list.hh"
55#include "cpu/o3/regfile.hh"
56#include "cpu/reg_class.hh"
1/*
2 * Copyright (c) 2015-2016 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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49#include <utility>
50#include <vector>
51
52#include "arch/types.hh"
53#include "config/the_isa.hh"
54#include "cpu/o3/free_list.hh"
55#include "cpu/o3/regfile.hh"
56#include "cpu/reg_class.hh"
57#include "enums/VecRegRenameMode.hh"
57
58/**
59 * Register rename map for a single class of registers (e.g., integer
60 * or floating point). Because the register class is implicitly
61 * determined by the rename map instance being accessed, all
62 * architectural register index parameters and values in this class
63 * are relative (e.g., %fp2 is just index 2).
64 */
65class SimpleRenameMap
66{
67 private:
68 using Arch2PhysMap = std::vector<PhysRegIdPtr>;
69 /** The acutal arch-to-phys register map */
70 Arch2PhysMap map;
58
59/**
60 * Register rename map for a single class of registers (e.g., integer
61 * or floating point). Because the register class is implicitly
62 * determined by the rename map instance being accessed, all
63 * architectural register index parameters and values in this class
64 * are relative (e.g., %fp2 is just index 2).
65 */
66class SimpleRenameMap
67{
68 private:
69 using Arch2PhysMap = std::vector<PhysRegIdPtr>;
70 /** The acutal arch-to-phys register map */
71 Arch2PhysMap map;
72 public:
73 using iterator = Arch2PhysMap::iterator;
74 using const_iterator = Arch2PhysMap::const_iterator;
75 private:
71
72 /**
73 * Pointer to the free list from which new physical registers
74 * should be allocated in rename()
75 */
76 SimpleFreeList *freeList;
77
78 /**

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134 void setEntry(const RegId& arch_reg, PhysRegIdPtr phys_reg)
135 {
136 assert(arch_reg.flatIndex() <= map.size());
137 map[arch_reg.flatIndex()] = phys_reg;
138 }
139
140 /** Return the number of free entries on the associated free list. */
141 unsigned numFreeEntries() const { return freeList->numFreeRegs(); }
76
77 /**
78 * Pointer to the free list from which new physical registers
79 * should be allocated in rename()
80 */
81 SimpleFreeList *freeList;
82
83 /**

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139 void setEntry(const RegId& arch_reg, PhysRegIdPtr phys_reg)
140 {
141 assert(arch_reg.flatIndex() <= map.size());
142 map[arch_reg.flatIndex()] = phys_reg;
143 }
144
145 /** Return the number of free entries on the associated free list. */
146 unsigned numFreeEntries() const { return freeList->numFreeRegs(); }
147
148 /** Forward begin/cbegin to the map. */
149 /** @{ */
150 iterator begin() { return map.begin(); }
151 const_iterator begin() const { return map.begin(); }
152 const_iterator cbegin() const { return map.cbegin(); }
153 /** @} */
154
155 /** Forward end/cend to the map. */
156 /** @{ */
157 iterator end() { return map.end(); }
158 const_iterator end() const { return map.end(); }
159 const_iterator cend() const { return map.cend(); }
160 /** @} */
142};
143
144
145/**
146 * Unified register rename map for all classes of registers. Wraps a
147 * set of class-specific rename maps. Methods that do not specify a
148 * register class (e.g., rename()) take register ids,
149 * while methods that do specify a register class (e.g., renameInt())
150 * take register indices.
151 */
152class UnifiedRenameMap
153{
154 private:
161};
162
163
164/**
165 * Unified register rename map for all classes of registers. Wraps a
166 * set of class-specific rename maps. Methods that do not specify a
167 * register class (e.g., rename()) take register ids,
168 * while methods that do specify a register class (e.g., renameInt())
169 * take register indices.
170 */
171class UnifiedRenameMap
172{
173 private:
174 static constexpr uint32_t NVecElems = TheISA::NumVecElemPerVecReg;
175 using VecReg = TheISA::VecReg;
155
156 /** The integer register rename map */
157 SimpleRenameMap intMap;
158
159 /** The floating-point register rename map */
160 SimpleRenameMap floatMap;
161
162 /** The condition-code register rename map */
163 SimpleRenameMap ccMap;
164
176
177 /** The integer register rename map */
178 SimpleRenameMap intMap;
179
180 /** The floating-point register rename map */
181 SimpleRenameMap floatMap;
182
183 /** The condition-code register rename map */
184 SimpleRenameMap ccMap;
185
186 /** The vector register rename map */
187 SimpleRenameMap vecMap;
188
189 /** The vector element register rename map */
190 SimpleRenameMap vecElemMap;
191
192 using VecMode = Enums::VecRegRenameMode;
193 VecMode vecMode;
194
165 /**
166 * The register file object is used only to get PhysRegIdPtr
167 * on MiscRegs, as they are stored in it.
168 */
169 PhysRegFile *regFile;
170
171 public:
172

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177
178 /** Destructor. */
179 ~UnifiedRenameMap() {};
180
181 /** Initializes rename map with given parameters. */
182 void init(PhysRegFile *_regFile,
183 RegIndex _intZeroReg,
184 RegIndex _floatZeroReg,
195 /**
196 * The register file object is used only to get PhysRegIdPtr
197 * on MiscRegs, as they are stored in it.
198 */
199 PhysRegFile *regFile;
200
201 public:
202

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207
208 /** Destructor. */
209 ~UnifiedRenameMap() {};
210
211 /** Initializes rename map with given parameters. */
212 void init(PhysRegFile *_regFile,
213 RegIndex _intZeroReg,
214 RegIndex _floatZeroReg,
185 UnifiedFreeList *freeList);
215 UnifiedFreeList *freeList,
216 VecMode _mode);
186
187 /**
188 * Tell rename map to get a new free physical register to remap
189 * the specified architectural register. This version takes a
190 * RegId and reads the appropriate class-specific rename table.
191 * @param arch_reg The architectural register id to remap.
192 * @return A RenameInfo pair indicating both the new and previous
193 * physical registers.
194 */
195 RenameInfo rename(const RegId& arch_reg)
196 {
197 switch (arch_reg.classValue()) {
198 case IntRegClass:
199 return intMap.rename(arch_reg);
200 case FloatRegClass:
201 return floatMap.rename(arch_reg);
217
218 /**
219 * Tell rename map to get a new free physical register to remap
220 * the specified architectural register. This version takes a
221 * RegId and reads the appropriate class-specific rename table.
222 * @param arch_reg The architectural register id to remap.
223 * @return A RenameInfo pair indicating both the new and previous
224 * physical registers.
225 */
226 RenameInfo rename(const RegId& arch_reg)
227 {
228 switch (arch_reg.classValue()) {
229 case IntRegClass:
230 return intMap.rename(arch_reg);
231 case FloatRegClass:
232 return floatMap.rename(arch_reg);
233 case VecRegClass:
234 assert(vecMode == Enums::Full);
235 return vecMap.rename(arch_reg);
236 case VecElemClass:
237 assert(vecMode == Enums::Elem);
238 return vecElemMap.rename(arch_reg);
202 case CCRegClass:
203 return ccMap.rename(arch_reg);
204 case MiscRegClass:
205 {
206 // misc regs aren't really renamed, just remapped
207 PhysRegIdPtr phys_reg = lookup(arch_reg);
208 // Set the new register to the previous one to keep the same
209 // mapping throughout the execution.

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227 {
228 switch (arch_reg.classValue()) {
229 case IntRegClass:
230 return intMap.lookup(arch_reg);
231
232 case FloatRegClass:
233 return floatMap.lookup(arch_reg);
234
239 case CCRegClass:
240 return ccMap.rename(arch_reg);
241 case MiscRegClass:
242 {
243 // misc regs aren't really renamed, just remapped
244 PhysRegIdPtr phys_reg = lookup(arch_reg);
245 // Set the new register to the previous one to keep the same
246 // mapping throughout the execution.

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264 {
265 switch (arch_reg.classValue()) {
266 case IntRegClass:
267 return intMap.lookup(arch_reg);
268
269 case FloatRegClass:
270 return floatMap.lookup(arch_reg);
271
272 case VecRegClass:
273 assert(vecMode == Enums::Full);
274 return vecMap.lookup(arch_reg);
275
276 case VecElemClass:
277 assert(vecMode == Enums::Elem);
278 return vecElemMap.lookup(arch_reg);
279
235 case CCRegClass:
236 return ccMap.lookup(arch_reg);
237
238 case MiscRegClass:
239 // misc regs aren't really renamed, they keep the same
240 // mapping throughout the execution.
241 return regFile->getMiscRegId(arch_reg.flatIndex());
242

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260 case IntRegClass:
261 assert(phys_reg->isIntPhysReg());
262 return intMap.setEntry(arch_reg, phys_reg);
263
264 case FloatRegClass:
265 assert(phys_reg->isFloatPhysReg());
266 return floatMap.setEntry(arch_reg, phys_reg);
267
280 case CCRegClass:
281 return ccMap.lookup(arch_reg);
282
283 case MiscRegClass:
284 // misc regs aren't really renamed, they keep the same
285 // mapping throughout the execution.
286 return regFile->getMiscRegId(arch_reg.flatIndex());
287

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305 case IntRegClass:
306 assert(phys_reg->isIntPhysReg());
307 return intMap.setEntry(arch_reg, phys_reg);
308
309 case FloatRegClass:
310 assert(phys_reg->isFloatPhysReg());
311 return floatMap.setEntry(arch_reg, phys_reg);
312
313 case VecRegClass:
314 assert(phys_reg->isVectorPhysReg());
315 assert(vecMode == Enums::Full);
316 return vecMap.setEntry(arch_reg, phys_reg);
317
318 case VecElemClass:
319 assert(phys_reg->isVectorPhysElem());
320 assert(vecMode == Enums::Elem);
321 return vecElemMap.setEntry(arch_reg, phys_reg);
322
268 case CCRegClass:
269 assert(phys_reg->isCCPhysReg());
270 return ccMap.setEntry(arch_reg, phys_reg);
271
272 case MiscRegClass:
273 // Misc registers do not actually rename, so don't change
274 // their mappings. We end up here when a commit or squash
275 // tries to update or undo a hardwired misc reg nmapping,

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286 /**
287 * Return the minimum number of free entries across all of the
288 * register classes. The minimum is used so we guarantee that
289 * this number of entries is available regardless of which class
290 * of registers is requested.
291 */
292 unsigned numFreeEntries() const
293 {
323 case CCRegClass:
324 assert(phys_reg->isCCPhysReg());
325 return ccMap.setEntry(arch_reg, phys_reg);
326
327 case MiscRegClass:
328 // Misc registers do not actually rename, so don't change
329 // their mappings. We end up here when a commit or squash
330 // tries to update or undo a hardwired misc reg nmapping,

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341 /**
342 * Return the minimum number of free entries across all of the
343 * register classes. The minimum is used so we guarantee that
344 * this number of entries is available regardless of which class
345 * of registers is requested.
346 */
347 unsigned numFreeEntries() const
348 {
294 return std::min(intMap.numFreeEntries(), floatMap.numFreeEntries());
349 return std::min(
350 std::min(intMap.numFreeEntries(), floatMap.numFreeEntries()),
351 vecMode == Enums::Full ? vecMap.numFreeEntries()
352 : vecElemMap.numFreeEntries());
295 }
296
353 }
354
355 unsigned numFreeIntEntries() const { return intMap.numFreeEntries(); }
356 unsigned numFreeFloatEntries() const { return floatMap.numFreeEntries(); }
357 unsigned numFreeVecEntries() const
358 {
359 return vecMode == Enums::Full
360 ? vecMap.numFreeEntries()
361 : vecElemMap.numFreeEntries();
362 }
363 unsigned numFreeCCEntries() const { return ccMap.numFreeEntries(); }
364
297 /**
298 * Return whether there are enough registers to serve the request.
299 */
365 /**
366 * Return whether there are enough registers to serve the request.
367 */
300 bool canRename(uint32_t intRegs, uint32_t floatRegs, uint32_t ccRegs) const
368 bool canRename(uint32_t intRegs, uint32_t floatRegs, uint32_t vectorRegs,
369 uint32_t vecElemRegs, uint32_t ccRegs) const
301 {
302 return intRegs <= intMap.numFreeEntries() &&
303 floatRegs <= floatMap.numFreeEntries() &&
370 {
371 return intRegs <= intMap.numFreeEntries() &&
372 floatRegs <= floatMap.numFreeEntries() &&
373 vectorRegs <= vecMap.numFreeEntries() &&
374 vecElemRegs <= vecElemMap.numFreeEntries() &&
304 ccRegs <= ccMap.numFreeEntries();
305 }
375 ccRegs <= ccMap.numFreeEntries();
376 }
377 /**
378 * Set vector mode to Full or Elem.
379 * Ignore 'silent' modifications.
380 */
381 void switchMode(VecMode newVecMode, UnifiedFreeList* freeList);
306
307};
308
309#endif //__CPU_O3_RENAME_MAP_HH__
382
383};
384
385#endif //__CPU_O3_RENAME_MAP_HH__