rename_map.hh (10934:5af8f40d8f2c) rename_map.hh (10935:acd48ddd725f)
1/*
2 * Copyright (c) 2015 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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173 * register indices that get passed in and handed out are of the
174 * proper class.
175 */
176 PhysRegFile *regFile;
177
178 /** The condition-code register rename map */
179 SimpleRenameMap ccMap;
180
1/*
2 * Copyright (c) 2015 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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173 * register indices that get passed in and handed out are of the
174 * proper class.
175 */
176 PhysRegFile *regFile;
177
178 /** The condition-code register rename map */
179 SimpleRenameMap ccMap;
180
181 /** The vector register rename map */
182 SimpleRenameMap vectorMap;
183
184 public:
185 typedef TheISA::RegIndex RegIndex;
186
187 typedef SimpleRenameMap::RenameInfo RenameInfo;
188
189 /** Default constructor. init() must be called prior to use. */
190 UnifiedRenameMap() : regFile(nullptr) {};
191

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238 RenameInfo renameCC(RegIndex rel_arch_reg)
239 {
240 RenameInfo info = ccMap.rename(rel_arch_reg);
241 assert(regFile->isCCPhysReg(info.first));
242 return info;
243 }
244
245 /**
181 public:
182 typedef TheISA::RegIndex RegIndex;
183
184 typedef SimpleRenameMap::RenameInfo RenameInfo;
185
186 /** Default constructor. init() must be called prior to use. */
187 UnifiedRenameMap() : regFile(nullptr) {};
188

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235 RenameInfo renameCC(RegIndex rel_arch_reg)
236 {
237 RenameInfo info = ccMap.rename(rel_arch_reg);
238 assert(regFile->isCCPhysReg(info.first));
239 return info;
240 }
241
242 /**
246 * Perform rename() on a vector register, given a relative vector register
247 * index.
248 */
249 RenameInfo renameVector(RegIndex rel_arch_reg)
250 {
251 RenameInfo info = vectorMap.rename(rel_arch_reg);
252 assert(regFile->isVectorPhysReg(info.first));
253 return info;
254 }
255
256 /**
257 * Perform rename() on a misc register, given a relative
258 * misc register index.
259 */
260 RenameInfo renameMisc(RegIndex rel_arch_reg)
261 {
262 // misc regs aren't really renamed, just remapped
263 PhysRegIndex phys_reg = lookupMisc(rel_arch_reg);
264 // Set the previous register to the same register; mainly it must be

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306 PhysRegIndex lookupCC(RegIndex rel_arch_reg) const
307 {
308 PhysRegIndex phys_reg = ccMap.lookup(rel_arch_reg);
309 assert(regFile->isCCPhysReg(phys_reg));
310 return phys_reg;
311 }
312
313 /**
243 * Perform rename() on a misc register, given a relative
244 * misc register index.
245 */
246 RenameInfo renameMisc(RegIndex rel_arch_reg)
247 {
248 // misc regs aren't really renamed, just remapped
249 PhysRegIndex phys_reg = lookupMisc(rel_arch_reg);
250 // Set the previous register to the same register; mainly it must be

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292 PhysRegIndex lookupCC(RegIndex rel_arch_reg) const
293 {
294 PhysRegIndex phys_reg = ccMap.lookup(rel_arch_reg);
295 assert(regFile->isCCPhysReg(phys_reg));
296 return phys_reg;
297 }
298
299 /**
314 * Perform lookup() on a vector register, given a relative
315 * vector register index.
316 */
317 PhysRegIndex lookupVector(RegIndex rel_arch_reg) const
318 {
319 PhysRegIndex phys_reg = vectorMap.lookup(rel_arch_reg);
320 assert(regFile->isVectorPhysReg(phys_reg));
321 return phys_reg;
322 }
323
324 /**
325 * Perform lookup() on a misc register, given a relative
326 * misc register index.
327 */
328 PhysRegIndex lookupMisc(RegIndex rel_arch_reg) const
329 {
330 // misc regs aren't really renamed, just given an index
331 // beyond the range of actual physical registers
332 PhysRegIndex phys_reg = rel_arch_reg + regFile->totalNumPhysRegs();

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369 */
370 void setCCEntry(RegIndex arch_reg, PhysRegIndex phys_reg)
371 {
372 assert(regFile->isCCPhysReg(phys_reg));
373 ccMap.setEntry(arch_reg, phys_reg);
374 }
375
376 /**
300 * Perform lookup() on a misc register, given a relative
301 * misc register index.
302 */
303 PhysRegIndex lookupMisc(RegIndex rel_arch_reg) const
304 {
305 // misc regs aren't really renamed, just given an index
306 // beyond the range of actual physical registers
307 PhysRegIndex phys_reg = rel_arch_reg + regFile->totalNumPhysRegs();

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344 */
345 void setCCEntry(RegIndex arch_reg, PhysRegIndex phys_reg)
346 {
347 assert(regFile->isCCPhysReg(phys_reg));
348 ccMap.setEntry(arch_reg, phys_reg);
349 }
350
351 /**
377 * Perform setEntry() on a vector register, given a relative vector
378 * register index.
379 */
380 void setVectorEntry(RegIndex arch_reg, PhysRegIndex phys_reg)
381 {
382 assert(regFile->isVectorPhysReg(phys_reg));
383 vectorMap.setEntry(arch_reg, phys_reg);
384 }
385
386 /**
387 * Return the minimum number of free entries across all of the
388 * register classes. The minimum is used so we guarantee that
389 * this number of entries is available regardless of which class
390 * of registers is requested.
391 */
392 unsigned numFreeEntries() const
393 {
394 return std::min(intMap.numFreeEntries(), floatMap.numFreeEntries());
395 }
396
397 /**
398 * Return whether there are enough registers to serve the request.
399 */
352 * Return the minimum number of free entries across all of the
353 * register classes. The minimum is used so we guarantee that
354 * this number of entries is available regardless of which class
355 * of registers is requested.
356 */
357 unsigned numFreeEntries() const
358 {
359 return std::min(intMap.numFreeEntries(), floatMap.numFreeEntries());
360 }
361
362 /**
363 * Return whether there are enough registers to serve the request.
364 */
400 bool canRename(uint32_t intRegs, uint32_t floatRegs, uint32_t ccRegs,
401 uint32_t vectorRegs) const
365 bool canRename(uint32_t intRegs, uint32_t floatRegs, uint32_t ccRegs) const
402 {
403 return intRegs <= intMap.numFreeEntries() &&
404 floatRegs <= floatMap.numFreeEntries() &&
366 {
367 return intRegs <= intMap.numFreeEntries() &&
368 floatRegs <= floatMap.numFreeEntries() &&
405 ccRegs <= ccMap.numFreeEntries() &&
406 vectorRegs <= vectorMap.numFreeEntries();
369 ccRegs <= ccMap.numFreeEntries();
407 }
408
409};
410
411#endif //__CPU_O3_RENAME_MAP_HH__
370 }
371
372};
373
374#endif //__CPU_O3_RENAME_MAP_HH__