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< * Copyright (c) 2015-2016 ARM Limited
---
> * Copyright (c) 2015-2017 ARM Limited
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> using VecPredReg = TheISA::VecPredReg;
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> /** The predicate register rename map */
> SimpleRenameMap predMap;
>
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> case VecPredRegClass:
> return predMap.rename(arch_reg);
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> case VecPredRegClass:
> return predMap.lookup(arch_reg);
>
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> case VecPredRegClass:
> assert(phys_reg->isVecPredPhysReg());
> return predMap.setEntry(arch_reg, phys_reg);
>
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< return std::min(
---
> return std::min(std::min(
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< : vecElemMap.numFreeEntries());
---
> : vecElemMap.numFreeEntries()),
> predMap.numFreeEntries());
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> unsigned numFreePredEntries() const { return predMap.numFreeEntries(); }
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< uint32_t vecElemRegs, uint32_t ccRegs) const
---
> uint32_t vecElemRegs, uint32_t vecPredRegs,
> uint32_t ccRegs) const
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> vecPredRegs <= predMap.numFreeEntries() &&