1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
| 1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 * 28 * Authors: Kevin Lim
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27 */ 28 29// Todo: Create destructor. 30// Have it so that there's a more meaningful name given to the variable 31// that marks the beginning of the FP registers. 32
| 29 */ 30 31// Todo: Create destructor. 32// Have it so that there's a more meaningful name given to the variable 33// that marks the beginning of the FP registers. 34
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33#ifndef __CPU_O3_RENAME_MAP_HH__ 34#define __CPU_O3_RENAME_MAP_HH__
| 35#ifndef __CPU_O3_CPU_RENAME_MAP_HH__ 36#define __CPU_O3_CPU_RENAME_MAP_HH__
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35 36#include <iostream> 37#include <utility> 38#include <vector> 39 40#include "cpu/o3/free_list.hh" 41//For RegIndex 42#include "arch/isa_traits.hh" 43 44class SimpleRenameMap 45{ 46 protected: 47 typedef TheISA::RegIndex RegIndex; 48 public: 49 /** 50 * Pair of a logical register and a physical register. Tells the 51 * previous mapping of a logical register to a physical register. 52 * Used to roll back the rename map to a previous state. 53 */ 54 typedef std::pair<RegIndex, PhysRegIndex> UnmapInfo; 55 56 /** 57 * Pair of a physical register and a physical register. Used to 58 * return the physical register that a logical register has been 59 * renamed to, and the previous physical register that the same 60 * logical register was previously mapped to. 61 */ 62 typedef std::pair<PhysRegIndex, PhysRegIndex> RenameInfo; 63 64 public: 65 //Constructor
| 37 38#include <iostream> 39#include <utility> 40#include <vector> 41 42#include "cpu/o3/free_list.hh" 43//For RegIndex 44#include "arch/isa_traits.hh" 45 46class SimpleRenameMap 47{ 48 protected: 49 typedef TheISA::RegIndex RegIndex; 50 public: 51 /** 52 * Pair of a logical register and a physical register. Tells the 53 * previous mapping of a logical register to a physical register. 54 * Used to roll back the rename map to a previous state. 55 */ 56 typedef std::pair<RegIndex, PhysRegIndex> UnmapInfo; 57 58 /** 59 * Pair of a physical register and a physical register. Used to 60 * return the physical register that a logical register has been 61 * renamed to, and the previous physical register that the same 62 * logical register was previously mapped to. 63 */ 64 typedef std::pair<PhysRegIndex, PhysRegIndex> RenameInfo; 65 66 public: 67 //Constructor
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66 SimpleRenameMap() {};
| 68 SimpleRenameMap(unsigned _numLogicalIntRegs, 69 unsigned _numPhysicalIntRegs, 70 unsigned _numLogicalFloatRegs, 71 unsigned _numPhysicalFloatRegs, 72 unsigned _numMiscRegs, 73 RegIndex _intZeroReg, 74 RegIndex _floatZeroReg);
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67 68 /** Destructor. */ 69 ~SimpleRenameMap(); 70
| 75 76 /** Destructor. */ 77 ~SimpleRenameMap(); 78
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71 void init(unsigned _numLogicalIntRegs, 72 unsigned _numPhysicalIntRegs, 73 PhysRegIndex &_int_reg_start, 74 75 unsigned _numLogicalFloatRegs, 76 unsigned _numPhysicalFloatRegs, 77 PhysRegIndex &_float_reg_start, 78 79 unsigned _numMiscRegs, 80 81 RegIndex _intZeroReg, 82 RegIndex _floatZeroReg, 83 84 int id, 85 bool bindRegs); 86
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87 void setFreeList(SimpleFreeList *fl_ptr); 88 89 //Tell rename map to get a free physical register for a given 90 //architected register. Not sure it should have a return value, 91 //but perhaps it should have some sort of fault in case there are 92 //no free registers. 93 RenameInfo rename(RegIndex arch_reg); 94 95 PhysRegIndex lookup(RegIndex phys_reg); 96
| 79 void setFreeList(SimpleFreeList *fl_ptr); 80 81 //Tell rename map to get a free physical register for a given 82 //architected register. Not sure it should have a return value, 83 //but perhaps it should have some sort of fault in case there are 84 //no free registers. 85 RenameInfo rename(RegIndex arch_reg); 86 87 PhysRegIndex lookup(RegIndex phys_reg); 88
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| 89 bool isReady(PhysRegIndex arch_reg); 90
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97 /** 98 * Marks the given register as ready, meaning that its value has been 99 * calculated and written to the register file. 100 * @param ready_reg The index of the physical register that is now ready. 101 */
| 91 /** 92 * Marks the given register as ready, meaning that its value has been 93 * calculated and written to the register file. 94 * @param ready_reg The index of the physical register that is now ready. 95 */
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| 96 void markAsReady(PhysRegIndex ready_reg); 97
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102 void setEntry(RegIndex arch_reg, PhysRegIndex renamed_reg); 103
| 98 void setEntry(RegIndex arch_reg, PhysRegIndex renamed_reg); 99
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| 100 void squash(std::vector<RegIndex> freed_regs, 101 std::vector<UnmapInfo> unmaps); 102
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104 int numFreeEntries(); 105 106 private:
| 103 int numFreeEntries(); 104 105 private:
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107 /** Rename Map ID */ 108 int id; 109
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110 /** Number of logical integer registers. */ 111 int numLogicalIntRegs; 112 113 /** Number of physical integer registers. */ 114 int numPhysicalIntRegs; 115 116 /** Number of logical floating point registers. */ 117 int numLogicalFloatRegs; 118 119 /** Number of physical floating point registers. */ 120 int numPhysicalFloatRegs; 121 122 /** Number of miscellaneous registers. */ 123 int numMiscRegs; 124 125 /** Number of logical integer + float registers. */ 126 int numLogicalRegs; 127 128 /** Number of physical integer + float registers. */ 129 int numPhysicalRegs; 130 131 /** The integer zero register. This implementation assumes it is always 132 * zero and never can be anything else. 133 */ 134 RegIndex intZeroReg; 135 136 /** The floating point zero register. This implementation assumes it is 137 * always zero and never can be anything else. 138 */ 139 RegIndex floatZeroReg; 140 141 class RenameEntry 142 { 143 public: 144 PhysRegIndex physical_reg; 145 bool valid; 146 147 RenameEntry() 148 : physical_reg(0), valid(false) 149 { } 150 }; 151
| 106 /** Number of logical integer registers. */ 107 int numLogicalIntRegs; 108 109 /** Number of physical integer registers. */ 110 int numPhysicalIntRegs; 111 112 /** Number of logical floating point registers. */ 113 int numLogicalFloatRegs; 114 115 /** Number of physical floating point registers. */ 116 int numPhysicalFloatRegs; 117 118 /** Number of miscellaneous registers. */ 119 int numMiscRegs; 120 121 /** Number of logical integer + float registers. */ 122 int numLogicalRegs; 123 124 /** Number of physical integer + float registers. */ 125 int numPhysicalRegs; 126 127 /** The integer zero register. This implementation assumes it is always 128 * zero and never can be anything else. 129 */ 130 RegIndex intZeroReg; 131 132 /** The floating point zero register. This implementation assumes it is 133 * always zero and never can be anything else. 134 */ 135 RegIndex floatZeroReg; 136 137 class RenameEntry 138 { 139 public: 140 PhysRegIndex physical_reg; 141 bool valid; 142 143 RenameEntry() 144 : physical_reg(0), valid(false) 145 { } 146 }; 147
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152 //Change this to private 153 private:
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154 /** Integer rename map. */
| 148 /** Integer rename map. */
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155 std::vector<RenameEntry> intRenameMap;
| 149 RenameEntry *intRenameMap;
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156 157 /** Floating point rename map. */
| 150 151 /** Floating point rename map. */
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158 std::vector<RenameEntry> floatRenameMap;
| 152 RenameEntry *floatRenameMap;
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159
| 153
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160 private:
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161 /** Free list interface. */ 162 SimpleFreeList *freeList;
| 154 /** Free list interface. */ 155 SimpleFreeList *freeList;
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| 156 157 // Might want to make all these scoreboards into one large scoreboard. 158 159 /** Scoreboard of physical integer registers, saying whether or not they 160 * are ready. 161 */ 162 std::vector<bool> intScoreboard; 163 164 /** Scoreboard of physical floating registers, saying whether or not they 165 * are ready. 166 */ 167 std::vector<bool> floatScoreboard; 168 169 /** Scoreboard of miscellaneous registers, saying whether or not they 170 * are ready. 171 */ 172 std::vector<bool> miscScoreboard;
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163}; 164
| 173}; 174
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165#endif //__CPU_O3_RENAME_MAP_HH__
| 175#endif //__CPU_O3_CPU_RENAME_MAP_HH__
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