1/*
2 * Copyright (c) 2015 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2005 The Regents of The University of Michigan
15 * Copyright (c) 2013 Advanced Micro Devices, Inc.
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 * Steve Reinhardt
43 */
44
45// Todo: Create destructor.
46// Have it so that there's a more meaningful name given to the variable
47// that marks the beginning of the FP registers.
48
49#ifndef __CPU_O3_RENAME_MAP_HH__
50#define __CPU_O3_RENAME_MAP_HH__
51
52#include <iostream>
53#include <utility>
54#include <vector>
55
56#include "arch/types.hh"
57#include "config/the_isa.hh"
58#include "cpu/o3/free_list.hh"
59#include "cpu/o3/regfile.hh"
60#include "cpu/reg_class.hh"
61
62/**
63 * Register rename map for a single class of registers (e.g., integer
64 * or floating point). Because the register class is implicitly
65 * determined by the rename map instance being accessed, all
66 * architectural register index parameters and values in this class
67 * are relative (e.g., %fp2 is just index 2).
68 */
69class SimpleRenameMap
70{
| 1/*
2 * Copyright (c) 2015 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2005 The Regents of The University of Michigan
15 * Copyright (c) 2013 Advanced Micro Devices, Inc.
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 * Steve Reinhardt
43 */
44
45// Todo: Create destructor.
46// Have it so that there's a more meaningful name given to the variable
47// that marks the beginning of the FP registers.
48
49#ifndef __CPU_O3_RENAME_MAP_HH__
50#define __CPU_O3_RENAME_MAP_HH__
51
52#include <iostream>
53#include <utility>
54#include <vector>
55
56#include "arch/types.hh"
57#include "config/the_isa.hh"
58#include "cpu/o3/free_list.hh"
59#include "cpu/o3/regfile.hh"
60#include "cpu/reg_class.hh"
61
62/**
63 * Register rename map for a single class of registers (e.g., integer
64 * or floating point). Because the register class is implicitly
65 * determined by the rename map instance being accessed, all
66 * architectural register index parameters and values in this class
67 * are relative (e.g., %fp2 is just index 2).
68 */
69class SimpleRenameMap
70{
|
71 public:
72
73 typedef TheISA::RegIndex RegIndex;
74
| |
75 private:
76
77 /** The acutal arch-to-phys register map */
78 std::vector<PhysRegIndex> map;
79
80 /**
81 * Pointer to the free list from which new physical registers
82 * should be allocated in rename()
83 */
84 SimpleFreeList *freeList;
85
86 /**
87 * The architectural index of the zero register. This register is
88 * mapped but read-only, so we ignore attempts to rename it via
89 * the rename() method. If there is no such register for this map
90 * table, it should be set to an invalid index so that it never
91 * matches.
92 */
93 RegIndex zeroReg;
94
95 public:
96
97 SimpleRenameMap();
98
99 ~SimpleRenameMap() {};
100
101 /**
102 * Because we have an array of rename maps (one per thread) in the CPU,
103 * it's awkward to initialize this object via the constructor.
104 * Instead, this method is used for initialization.
105 */
106 void init(unsigned size, SimpleFreeList *_freeList, RegIndex _zeroReg);
107
108 /**
109 * Pair of a physical register and a physical register. Used to
110 * return the physical register that a logical register has been
111 * renamed to, and the previous physical register that the same
112 * logical register was previously mapped to.
113 */
114 typedef std::pair<PhysRegIndex, PhysRegIndex> RenameInfo;
115
116 /**
117 * Tell rename map to get a new free physical register to remap
118 * the specified architectural register.
119 * @param arch_reg The architectural register to remap.
120 * @return A RenameInfo pair indicating both the new and previous
121 * physical registers.
122 */
123 RenameInfo rename(RegIndex arch_reg);
124
125 /**
126 * Look up the physical register mapped to an architectural register.
127 * @param arch_reg The architectural register to look up.
128 * @return The physical register it is currently mapped to.
129 */
130 PhysRegIndex lookup(RegIndex arch_reg) const
131 {
132 assert(arch_reg < map.size());
133 return map[arch_reg];
134 }
135
136 /**
137 * Update rename map with a specific mapping. Generally used to
138 * roll back to old mappings on a squash.
139 * @param arch_reg The architectural register to remap.
140 * @param phys_reg The physical register to remap it to.
141 */
142 void setEntry(RegIndex arch_reg, PhysRegIndex phys_reg)
143 {
144 map[arch_reg] = phys_reg;
145 }
146
147 /** Return the number of free entries on the associated free list. */
148 unsigned numFreeEntries() const { return freeList->numFreeRegs(); }
149};
150
151
152/**
153 * Unified register rename map for all classes of registers. Wraps a
154 * set of class-specific rename maps. Methods that do not specify a
| 71 private:
72
73 /** The acutal arch-to-phys register map */
74 std::vector<PhysRegIndex> map;
75
76 /**
77 * Pointer to the free list from which new physical registers
78 * should be allocated in rename()
79 */
80 SimpleFreeList *freeList;
81
82 /**
83 * The architectural index of the zero register. This register is
84 * mapped but read-only, so we ignore attempts to rename it via
85 * the rename() method. If there is no such register for this map
86 * table, it should be set to an invalid index so that it never
87 * matches.
88 */
89 RegIndex zeroReg;
90
91 public:
92
93 SimpleRenameMap();
94
95 ~SimpleRenameMap() {};
96
97 /**
98 * Because we have an array of rename maps (one per thread) in the CPU,
99 * it's awkward to initialize this object via the constructor.
100 * Instead, this method is used for initialization.
101 */
102 void init(unsigned size, SimpleFreeList *_freeList, RegIndex _zeroReg);
103
104 /**
105 * Pair of a physical register and a physical register. Used to
106 * return the physical register that a logical register has been
107 * renamed to, and the previous physical register that the same
108 * logical register was previously mapped to.
109 */
110 typedef std::pair<PhysRegIndex, PhysRegIndex> RenameInfo;
111
112 /**
113 * Tell rename map to get a new free physical register to remap
114 * the specified architectural register.
115 * @param arch_reg The architectural register to remap.
116 * @return A RenameInfo pair indicating both the new and previous
117 * physical registers.
118 */
119 RenameInfo rename(RegIndex arch_reg);
120
121 /**
122 * Look up the physical register mapped to an architectural register.
123 * @param arch_reg The architectural register to look up.
124 * @return The physical register it is currently mapped to.
125 */
126 PhysRegIndex lookup(RegIndex arch_reg) const
127 {
128 assert(arch_reg < map.size());
129 return map[arch_reg];
130 }
131
132 /**
133 * Update rename map with a specific mapping. Generally used to
134 * roll back to old mappings on a squash.
135 * @param arch_reg The architectural register to remap.
136 * @param phys_reg The physical register to remap it to.
137 */
138 void setEntry(RegIndex arch_reg, PhysRegIndex phys_reg)
139 {
140 map[arch_reg] = phys_reg;
141 }
142
143 /** Return the number of free entries on the associated free list. */
144 unsigned numFreeEntries() const { return freeList->numFreeRegs(); }
145};
146
147
148/**
149 * Unified register rename map for all classes of registers. Wraps a
150 * set of class-specific rename maps. Methods that do not specify a
|
155 * register class (e.g., rename()) take unified register indices,
| 151 * register class (e.g., rename()) take register ids,
|
156 * while methods that do specify a register class (e.g., renameInt())
| 152 * while methods that do specify a register class (e.g., renameInt())
|
157 * take relative register indices. See http://gem5.org/Register_Indexing.
| 153 * take register indices.
|
158 */
159class UnifiedRenameMap
160{
161 private:
162
163 /** The integer register rename map */
164 SimpleRenameMap intMap;
165
166 /** The floating-point register rename map */
167 SimpleRenameMap floatMap;
168
169 /**
170 * The register file object is used only to distinguish integer
171 * from floating-point physical register indices, which in turn is
172 * used only for assert statements that make sure the physical
173 * register indices that get passed in and handed out are of the
174 * proper class.
175 */
176 PhysRegFile *regFile;
177
178 /** The condition-code register rename map */
179 SimpleRenameMap ccMap;
180
181 public:
| 154 */
155class UnifiedRenameMap
156{
157 private:
158
159 /** The integer register rename map */
160 SimpleRenameMap intMap;
161
162 /** The floating-point register rename map */
163 SimpleRenameMap floatMap;
164
165 /**
166 * The register file object is used only to distinguish integer
167 * from floating-point physical register indices, which in turn is
168 * used only for assert statements that make sure the physical
169 * register indices that get passed in and handed out are of the
170 * proper class.
171 */
172 PhysRegFile *regFile;
173
174 /** The condition-code register rename map */
175 SimpleRenameMap ccMap;
176
177 public:
|
182 typedef TheISA::RegIndex RegIndex;
| |
183
184 typedef SimpleRenameMap::RenameInfo RenameInfo;
185
186 /** Default constructor. init() must be called prior to use. */
187 UnifiedRenameMap() : regFile(nullptr) {};
188
189 /** Destructor. */
190 ~UnifiedRenameMap() {};
191
192 /** Initializes rename map with given parameters. */
193 void init(PhysRegFile *_regFile,
194 RegIndex _intZeroReg,
195 RegIndex _floatZeroReg,
196 UnifiedFreeList *freeList);
197
198 /**
199 * Tell rename map to get a new free physical register to remap
| 178
179 typedef SimpleRenameMap::RenameInfo RenameInfo;
180
181 /** Default constructor. init() must be called prior to use. */
182 UnifiedRenameMap() : regFile(nullptr) {};
183
184 /** Destructor. */
185 ~UnifiedRenameMap() {};
186
187 /** Initializes rename map with given parameters. */
188 void init(PhysRegFile *_regFile,
189 RegIndex _intZeroReg,
190 RegIndex _floatZeroReg,
191 UnifiedFreeList *freeList);
192
193 /**
194 * Tell rename map to get a new free physical register to remap
|
200 * the specified architectural register. This version takes a
201 * unified flattened architectural register index and calls the
| 195 * the specified architectural register. This version takes a
196 * flattened architectural register id and calls the
|
202 * appropriate class-specific rename table.
| 197 * appropriate class-specific rename table.
|
203 * @param arch_reg The unified architectural register index to remap.
| 198 * @param arch_reg The architectural register index to remap.
|
204 * @return A RenameInfo pair indicating both the new and previous
205 * physical registers.
206 */
| 199 * @return A RenameInfo pair indicating both the new and previous
200 * physical registers.
201 */
|
207 RenameInfo rename(RegIndex arch_reg);
| 202 RenameInfo rename(RegId arch_reg);
|
208
209 /**
| 203
204 /**
|
210 * Perform rename() on an integer register, given a relative
| 205 * Perform rename() on an integer register, given a
|
211 * integer register index.
212 */
213 RenameInfo renameInt(RegIndex rel_arch_reg)
214 {
215 RenameInfo info = intMap.rename(rel_arch_reg);
216 assert(regFile->isIntPhysReg(info.first));
217 return info;
218 }
219
220 /**
| 206 * integer register index.
207 */
208 RenameInfo renameInt(RegIndex rel_arch_reg)
209 {
210 RenameInfo info = intMap.rename(rel_arch_reg);
211 assert(regFile->isIntPhysReg(info.first));
212 return info;
213 }
214
215 /**
|
221 * Perform rename() on a floating-point register, given a relative
| 216 * Perform rename() on a floating-point register, given a
|
222 * floating-point register index.
223 */
224 RenameInfo renameFloat(RegIndex rel_arch_reg)
225 {
226 RenameInfo info = floatMap.rename(rel_arch_reg);
227 assert(regFile->isFloatPhysReg(info.first));
228 return info;
229 }
230
231 /**
| 217 * floating-point register index.
218 */
219 RenameInfo renameFloat(RegIndex rel_arch_reg)
220 {
221 RenameInfo info = floatMap.rename(rel_arch_reg);
222 assert(regFile->isFloatPhysReg(info.first));
223 return info;
224 }
225
226 /**
|
232 * Perform rename() on a condition-code register, given a relative
| 227 * Perform rename() on a condition-code register, given a
|
233 * condition-code register index.
234 */
235 RenameInfo renameCC(RegIndex rel_arch_reg)
236 {
237 RenameInfo info = ccMap.rename(rel_arch_reg);
238 assert(regFile->isCCPhysReg(info.first));
239 return info;
240 }
241
242 /**
| 228 * condition-code register index.
229 */
230 RenameInfo renameCC(RegIndex rel_arch_reg)
231 {
232 RenameInfo info = ccMap.rename(rel_arch_reg);
233 assert(regFile->isCCPhysReg(info.first));
234 return info;
235 }
236
237 /**
|
243 * Perform rename() on a misc register, given a relative
| 238 * Perform rename() on a misc register, given a
|
244 * misc register index.
245 */
246 RenameInfo renameMisc(RegIndex rel_arch_reg)
247 {
248 // misc regs aren't really renamed, just remapped
249 PhysRegIndex phys_reg = lookupMisc(rel_arch_reg);
250 // Set the previous register to the same register; mainly it must be
251 // known that the prev reg was outside the range of normal registers
252 // so the free list can avoid adding it.
253 return RenameInfo(phys_reg, phys_reg);
254 }
255
256
257 /**
258 * Look up the physical register mapped to an architectural register.
| 239 * misc register index.
240 */
241 RenameInfo renameMisc(RegIndex rel_arch_reg)
242 {
243 // misc regs aren't really renamed, just remapped
244 PhysRegIndex phys_reg = lookupMisc(rel_arch_reg);
245 // Set the previous register to the same register; mainly it must be
246 // known that the prev reg was outside the range of normal registers
247 // so the free list can avoid adding it.
248 return RenameInfo(phys_reg, phys_reg);
249 }
250
251
252 /**
253 * Look up the physical register mapped to an architectural register.
|
259 * This version takes a unified flattened architectural register index
| 254 * This version takes a flattened architectural register id
|
260 * and calls the appropriate class-specific rename table.
| 255 * and calls the appropriate class-specific rename table.
|
261 * @param arch_reg The unified architectural register to look up.
| 256 * @param arch_reg The architectural register to look up.
|
262 * @return The physical register it is currently mapped to.
263 */
| 257 * @return The physical register it is currently mapped to.
258 */
|
264 PhysRegIndex lookup(RegIndex arch_reg) const;
| 259 PhysRegIndex lookup(RegId arch_reg) const;
|
265
266 /**
| 260
261 /**
|
267 * Perform lookup() on an integer register, given a relative
| 262 * Perform lookup() on an integer register, given a
|
268 * integer register index.
269 */
270 PhysRegIndex lookupInt(RegIndex rel_arch_reg) const
271 {
272 PhysRegIndex phys_reg = intMap.lookup(rel_arch_reg);
273 assert(regFile->isIntPhysReg(phys_reg));
274 return phys_reg;
275 }
276
277 /**
| 263 * integer register index.
264 */
265 PhysRegIndex lookupInt(RegIndex rel_arch_reg) const
266 {
267 PhysRegIndex phys_reg = intMap.lookup(rel_arch_reg);
268 assert(regFile->isIntPhysReg(phys_reg));
269 return phys_reg;
270 }
271
272 /**
|
278 * Perform lookup() on a floating-point register, given a relative
| 273 * Perform lookup() on a floating-point register, given a
|
279 * floating-point register index.
280 */
281 PhysRegIndex lookupFloat(RegIndex rel_arch_reg) const
282 {
283 PhysRegIndex phys_reg = floatMap.lookup(rel_arch_reg);
284 assert(regFile->isFloatPhysReg(phys_reg));
285 return phys_reg;
286 }
287
288 /**
| 274 * floating-point register index.
275 */
276 PhysRegIndex lookupFloat(RegIndex rel_arch_reg) const
277 {
278 PhysRegIndex phys_reg = floatMap.lookup(rel_arch_reg);
279 assert(regFile->isFloatPhysReg(phys_reg));
280 return phys_reg;
281 }
282
283 /**
|
289 * Perform lookup() on a condition-code register, given a relative
| 284 * Perform lookup() on a condition-code register, given a
|
290 * condition-code register index.
291 */
292 PhysRegIndex lookupCC(RegIndex rel_arch_reg) const
293 {
294 PhysRegIndex phys_reg = ccMap.lookup(rel_arch_reg);
295 assert(regFile->isCCPhysReg(phys_reg));
296 return phys_reg;
297 }
298
299 /**
300 * Perform lookup() on a misc register, given a relative
301 * misc register index.
302 */
303 PhysRegIndex lookupMisc(RegIndex rel_arch_reg) const
304 {
305 // misc regs aren't really renamed, just given an index
306 // beyond the range of actual physical registers
307 PhysRegIndex phys_reg = rel_arch_reg + regFile->totalNumPhysRegs();
308 return phys_reg;
309 }
310
311 /**
312 * Update rename map with a specific mapping. Generally used to
313 * roll back to old mappings on a squash. This version takes a
| 285 * condition-code register index.
286 */
287 PhysRegIndex lookupCC(RegIndex rel_arch_reg) const
288 {
289 PhysRegIndex phys_reg = ccMap.lookup(rel_arch_reg);
290 assert(regFile->isCCPhysReg(phys_reg));
291 return phys_reg;
292 }
293
294 /**
295 * Perform lookup() on a misc register, given a relative
296 * misc register index.
297 */
298 PhysRegIndex lookupMisc(RegIndex rel_arch_reg) const
299 {
300 // misc regs aren't really renamed, just given an index
301 // beyond the range of actual physical registers
302 PhysRegIndex phys_reg = rel_arch_reg + regFile->totalNumPhysRegs();
303 return phys_reg;
304 }
305
306 /**
307 * Update rename map with a specific mapping. Generally used to
308 * roll back to old mappings on a squash. This version takes a
|
314 * unified flattened architectural register index and calls the
| 309 * flattened architectural register id and calls the
|
315 * appropriate class-specific rename table.
| 310 * appropriate class-specific rename table.
|
316 * @param arch_reg The unified architectural register to remap.
| 311 * @param arch_reg The architectural register to remap.
|
317 * @param phys_reg The physical register to remap it to.
318 */
| 312 * @param phys_reg The physical register to remap it to.
313 */
|
319 void setEntry(RegIndex arch_reg, PhysRegIndex phys_reg);
| 314 void setEntry(RegId arch_reg, PhysRegIndex phys_reg);
|
320
321 /**
| 315
316 /**
|
322 * Perform setEntry() on an integer register, given a relative
| 317 * Perform setEntry() on an integer register, given a
|
323 * integer register index.
324 */
325 void setIntEntry(RegIndex arch_reg, PhysRegIndex phys_reg)
326 {
327 assert(regFile->isIntPhysReg(phys_reg));
328 intMap.setEntry(arch_reg, phys_reg);
329 }
330
331 /**
| 318 * integer register index.
319 */
320 void setIntEntry(RegIndex arch_reg, PhysRegIndex phys_reg)
321 {
322 assert(regFile->isIntPhysReg(phys_reg));
323 intMap.setEntry(arch_reg, phys_reg);
324 }
325
326 /**
|
332 * Perform setEntry() on a floating-point register, given a relative
| 327 * Perform setEntry() on a floating-point register, given a
|
333 * floating-point register index.
334 */
335 void setFloatEntry(RegIndex arch_reg, PhysRegIndex phys_reg)
336 {
337 assert(regFile->isFloatPhysReg(phys_reg));
338 floatMap.setEntry(arch_reg, phys_reg);
339 }
340
341 /**
| 328 * floating-point register index.
329 */
330 void setFloatEntry(RegIndex arch_reg, PhysRegIndex phys_reg)
331 {
332 assert(regFile->isFloatPhysReg(phys_reg));
333 floatMap.setEntry(arch_reg, phys_reg);
334 }
335
336 /**
|
342 * Perform setEntry() on a condition-code register, given a relative
| 337 * Perform setEntry() on a condition-code register, given a
|
343 * condition-code register index.
344 */
345 void setCCEntry(RegIndex arch_reg, PhysRegIndex phys_reg)
346 {
347 assert(regFile->isCCPhysReg(phys_reg));
348 ccMap.setEntry(arch_reg, phys_reg);
349 }
350
351 /**
352 * Return the minimum number of free entries across all of the
353 * register classes. The minimum is used so we guarantee that
354 * this number of entries is available regardless of which class
355 * of registers is requested.
356 */
357 unsigned numFreeEntries() const
358 {
359 return std::min(intMap.numFreeEntries(), floatMap.numFreeEntries());
360 }
361
362 /**
363 * Return whether there are enough registers to serve the request.
364 */
365 bool canRename(uint32_t intRegs, uint32_t floatRegs, uint32_t ccRegs) const
366 {
367 return intRegs <= intMap.numFreeEntries() &&
368 floatRegs <= floatMap.numFreeEntries() &&
369 ccRegs <= ccMap.numFreeEntries();
370 }
371
372};
373
374#endif //__CPU_O3_RENAME_MAP_HH__
| 338 * condition-code register index.
339 */
340 void setCCEntry(RegIndex arch_reg, PhysRegIndex phys_reg)
341 {
342 assert(regFile->isCCPhysReg(phys_reg));
343 ccMap.setEntry(arch_reg, phys_reg);
344 }
345
346 /**
347 * Return the minimum number of free entries across all of the
348 * register classes. The minimum is used so we guarantee that
349 * this number of entries is available regardless of which class
350 * of registers is requested.
351 */
352 unsigned numFreeEntries() const
353 {
354 return std::min(intMap.numFreeEntries(), floatMap.numFreeEntries());
355 }
356
357 /**
358 * Return whether there are enough registers to serve the request.
359 */
360 bool canRename(uint32_t intRegs, uint32_t floatRegs, uint32_t ccRegs) const
361 {
362 return intRegs <= intMap.numFreeEntries() &&
363 floatRegs <= floatMap.numFreeEntries() &&
364 ccRegs <= ccMap.numFreeEntries();
365 }
366
367};
368
369#endif //__CPU_O3_RENAME_MAP_HH__
|