1/*
2 * Copyright (c) 2015-2016 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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167 * while methods that do specify a register class (e.g., renameInt())
168 * take register indices.
169 */
170class UnifiedRenameMap
171{
172 private:
173 static constexpr uint32_t NVecElems = TheISA::NumVecElemPerVecReg;
174 using VecReg = TheISA::VecReg;
175
176 /** The integer register rename map */
177 SimpleRenameMap intMap;
178
179 /** The floating-point register rename map */
180 SimpleRenameMap floatMap;
181
182 /** The condition-code register rename map */
183 SimpleRenameMap ccMap;
184
185 /** The vector register rename map */
186 SimpleRenameMap vecMap;
187
188 /** The vector element register rename map */
189 SimpleRenameMap vecElemMap;
190
191 using VecMode = Enums::VecRegRenameMode;
192 VecMode vecMode;
193
194 /**
195 * The register file object is used only to get PhysRegIdPtr
196 * on MiscRegs, as they are stored in it.
197 */
198 PhysRegFile *regFile;

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230 case FloatRegClass:
231 return floatMap.rename(arch_reg);
232 case VecRegClass:
233 assert(vecMode == Enums::Full);
234 return vecMap.rename(arch_reg);
235 case VecElemClass:
236 assert(vecMode == Enums::Elem);
237 return vecElemMap.rename(arch_reg);
238 case CCRegClass:
239 return ccMap.rename(arch_reg);
240 case MiscRegClass:
241 {
242 // misc regs aren't really renamed, just remapped
243 PhysRegIdPtr phys_reg = lookup(arch_reg);
244 // Set the new register to the previous one to keep the same
245 // mapping throughout the execution.

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271 case VecRegClass:
272 assert(vecMode == Enums::Full);
273 return vecMap.lookup(arch_reg);
274
275 case VecElemClass:
276 assert(vecMode == Enums::Elem);
277 return vecElemMap.lookup(arch_reg);
278
279 case CCRegClass:
280 return ccMap.lookup(arch_reg);
281
282 case MiscRegClass:
283 // misc regs aren't really renamed, they keep the same
284 // mapping throughout the execution.
285 return regFile->getMiscRegId(arch_reg.flatIndex());
286

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314 assert(vecMode == Enums::Full);
315 return vecMap.setEntry(arch_reg, phys_reg);
316
317 case VecElemClass:
318 assert(phys_reg->isVectorPhysElem());
319 assert(vecMode == Enums::Elem);
320 return vecElemMap.setEntry(arch_reg, phys_reg);
321
322 case CCRegClass:
323 assert(phys_reg->isCCPhysReg());
324 return ccMap.setEntry(arch_reg, phys_reg);
325
326 case MiscRegClass:
327 // Misc registers do not actually rename, so don't change
328 // their mappings. We end up here when a commit or squash
329 // tries to update or undo a hardwired misc reg nmapping,

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340 /**
341 * Return the minimum number of free entries across all of the
342 * register classes. The minimum is used so we guarantee that
343 * this number of entries is available regardless of which class
344 * of registers is requested.
345 */
346 unsigned numFreeEntries() const
347 {
348 return std::min(
349 std::min(intMap.numFreeEntries(), floatMap.numFreeEntries()),
350 vecMode == Enums::Full ? vecMap.numFreeEntries()
351 : vecElemMap.numFreeEntries());
352 }
353
354 unsigned numFreeIntEntries() const { return intMap.numFreeEntries(); }
355 unsigned numFreeFloatEntries() const { return floatMap.numFreeEntries(); }
356 unsigned numFreeVecEntries() const
357 {
358 return vecMode == Enums::Full
359 ? vecMap.numFreeEntries()
360 : vecElemMap.numFreeEntries();
361 }
362 unsigned numFreeCCEntries() const { return ccMap.numFreeEntries(); }
363
364 /**
365 * Return whether there are enough registers to serve the request.
366 */
367 bool canRename(uint32_t intRegs, uint32_t floatRegs, uint32_t vectorRegs,
368 uint32_t vecElemRegs, uint32_t ccRegs) const
369 {
370 return intRegs <= intMap.numFreeEntries() &&
371 floatRegs <= floatMap.numFreeEntries() &&
372 vectorRegs <= vecMap.numFreeEntries() &&
373 vecElemRegs <= vecElemMap.numFreeEntries() &&
374 ccRegs <= ccMap.numFreeEntries();
375 }
376 /**
377 * Set vector mode to Full or Elem.
378 * Ignore 'silent' modifications.
379 *
380 * @param newVecMode new vector renaming mode
381 */
382 void switchMode(VecMode newVecMode);
383
384 /**
385 * Switch freeList of registers from Full to Elem or vicevers
386 * depending on vecMode (vector renaming mode).
387 */
388 void switchFreeList(UnifiedFreeList* freeList);
389
390};
391
392#endif //__CPU_O3_RENAME_MAP_HH__