1/*
2 * Copyright (c) 2015 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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60 * or floating point). Because the register class is implicitly
61 * determined by the rename map instance being accessed, all
62 * architectural register index parameters and values in this class
63 * are relative (e.g., %fp2 is just index 2).
64 */
65class SimpleRenameMap
66{
67 private:
68
69 /** The acutal arch-to-phys register map */
70 std::vector<PhysRegIdPtr> map;
71
72 /**
73 * Pointer to the free list from which new physical registers
74 * should be allocated in rename()
75 */
76 SimpleFreeList *freeList;
77
78 /**
79 * The architectural index of the zero register. This register is
80 * mapped but read-only, so we ignore attempts to rename it via
81 * the rename() method. If there is no such register for this map
82 * table, it should be set to an invalid index so that it never
83 * matches.
84 */
85 RegIndex zeroReg;
86
87 public:
88
89 SimpleRenameMap();
90
91 ~SimpleRenameMap() {};
92
93 /**

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107
108 /**
109 * Tell rename map to get a new free physical register to remap
110 * the specified architectural register.
111 * @param arch_reg The architectural register to remap.
112 * @return A RenameInfo pair indicating both the new and previous
113 * physical registers.
114 */
115 RenameInfo rename(RegIndex arch_reg);
116
117 /**
118 * Look up the physical register mapped to an architectural register.
119 * @param arch_reg The architectural register to look up.
120 * @return The physical register it is currently mapped to.
121 */
122 PhysRegIdPtr lookup(RegIndex arch_reg) const
123 {
124 assert(arch_reg < map.size());
125 return map[arch_reg];
126 }
127
128 /**
129 * Update rename map with a specific mapping. Generally used to
130 * roll back to old mappings on a squash.
131 * @param arch_reg The architectural register to remap.
132 * @param phys_reg The physical register to remap it to.
133 */
134 void setEntry(RegIndex arch_reg, PhysRegIdPtr phys_reg)
135 {
136 map[arch_reg] = phys_reg;
137 }
138
139 /** Return the number of free entries on the associated free list. */
140 unsigned numFreeEntries() const { return freeList->numFreeRegs(); }
141};
142
143
144/**

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181 void init(PhysRegFile *_regFile,
182 RegIndex _intZeroReg,
183 RegIndex _floatZeroReg,
184 UnifiedFreeList *freeList);
185
186 /**
187 * Tell rename map to get a new free physical register to remap
188 * the specified architectural register. This version takes a
189 * flattened architectural register id and calls the
190 * appropriate class-specific rename table.
191 * @param arch_reg The architectural register index to remap.
192 * @return A RenameInfo pair indicating both the new and previous
193 * physical registers.
194 */
195 RenameInfo rename(RegId arch_reg);
196
197 /**
198 * Perform rename() on an integer register, given a
199 * integer register index.
200 */
201 RenameInfo renameInt(RegIndex rel_arch_reg)
202 {
203 return intMap.rename(rel_arch_reg);
204 }
205
206 /**
207 * Perform rename() on a floating-point register, given a
208 * floating-point register index.
209 */
210 RenameInfo renameFloat(RegIndex rel_arch_reg)
211 {
212 return floatMap.rename(rel_arch_reg);
213 }
214
215 /**
216 * Perform rename() on a condition-code register, given a
217 * condition-code register index.
218 */
219 RenameInfo renameCC(RegIndex rel_arch_reg)
220 {
221 return ccMap.rename(rel_arch_reg);
222 }
223
224 /**
225 * Perform rename() on a misc register, given a
226 * misc register index.
227 */
228 RenameInfo renameMisc(RegIndex rel_arch_reg)
229 {
230 // misc regs aren't really renamed, just remapped
231 PhysRegIdPtr phys_reg = lookupMisc(rel_arch_reg);
232 // Set the new register to the previous one to keep the same
233 // mapping throughout the execution.
234 return RenameInfo(phys_reg, phys_reg);
235 }
236
237
238 /**
239 * Look up the physical register mapped to an architectural register.
240 * This version takes a flattened architectural register id
241 * and calls the appropriate class-specific rename table.
242 * @param arch_reg The architectural register to look up.
243 * @return The physical register it is currently mapped to.
244 */
245 PhysRegIdPtr lookup(RegId arch_reg) const;
246
247 /**
248 * Perform lookup() on an integer register, given a
249 * integer register index.
250 */
251 PhysRegIdPtr lookupInt(RegIndex rel_arch_reg) const
252 {
253 return intMap.lookup(rel_arch_reg);
254 }
255
256 /**
257 * Perform lookup() on a floating-point register, given a
258 * floating-point register index.
259 */
260 PhysRegIdPtr lookupFloat(RegIndex rel_arch_reg) const
261 {
262 return floatMap.lookup(rel_arch_reg);
263 }
264
265 /**
266 * Perform lookup() on a condition-code register, given a
267 * condition-code register index.
268 */
269 PhysRegIdPtr lookupCC(RegIndex rel_arch_reg) const
270 {
271 return ccMap.lookup(rel_arch_reg);
272 }
273
274 /**
275 * Perform lookup() on a misc register, given a relative
276 * misc register index.
277 */
278 PhysRegIdPtr lookupMisc(RegIndex rel_arch_reg) const
279 {
280 // misc regs aren't really renamed, they keep the same
281 // mapping throughout the execution.
282 return regFile->getMiscRegId(rel_arch_reg);
283 }
284
285 /**
286 * Update rename map with a specific mapping. Generally used to
287 * roll back to old mappings on a squash. This version takes a
288 * flattened architectural register id and calls the
289 * appropriate class-specific rename table.
290 * @param arch_reg The architectural register to remap.
291 * @param phys_reg The physical register to remap it to.
292 */
293 void setEntry(RegId arch_reg, PhysRegIdPtr phys_reg);
294
295 /**
296 * Perform setEntry() on an integer register, given a
297 * integer register index.
298 */
299 void setIntEntry(RegIndex arch_reg, PhysRegIdPtr phys_reg)
300 {
301 assert(phys_reg->isIntPhysReg());
302 intMap.setEntry(arch_reg, phys_reg);
303 }
304
305 /**
306 * Perform setEntry() on a floating-point register, given a
307 * floating-point register index.
308 */
309 void setFloatEntry(RegIndex arch_reg, PhysRegIdPtr phys_reg)
310 {
311 assert(phys_reg->isFloatPhysReg());
312 floatMap.setEntry(arch_reg, phys_reg);
313 }
314
315 /**
316 * Perform setEntry() on a condition-code register, given a
317 * condition-code register index.
318 */
319 void setCCEntry(RegIndex arch_reg, PhysRegIdPtr phys_reg)
320 {
321 assert(phys_reg->isCCPhysReg());
322 ccMap.setEntry(arch_reg, phys_reg);
323 }
324
325 /**
326 * Return the minimum number of free entries across all of the
327 * register classes. The minimum is used so we guarantee that
328 * this number of entries is available regardless of which class
329 * of registers is requested.
330 */

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