1/*
2 * Copyright (c) 2015-2017 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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167 * while methods that do specify a register class (e.g., renameInt())
168 * take register indices.
169 */
170class UnifiedRenameMap
171{
172 private:
173 static constexpr uint32_t NVecElems = TheISA::NumVecElemPerVecReg;
174 using VecReg = TheISA::VecReg;
175 using VecPredReg = TheISA::VecPredReg;
176
177 /** The integer register rename map */
178 SimpleRenameMap intMap;
179
180 /** The floating-point register rename map */
181 SimpleRenameMap floatMap;
182
183 /** The condition-code register rename map */
184 SimpleRenameMap ccMap;
185
186 /** The vector register rename map */
187 SimpleRenameMap vecMap;
188
189 /** The vector element register rename map */
190 SimpleRenameMap vecElemMap;
191
192 /** The predicate register rename map */
193 SimpleRenameMap predMap;
194
195 using VecMode = Enums::VecRegRenameMode;
196 VecMode vecMode;
197
198 /**
199 * The register file object is used only to get PhysRegIdPtr
200 * on MiscRegs, as they are stored in it.
201 */
202 PhysRegFile *regFile;

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234 case FloatRegClass:
235 return floatMap.rename(arch_reg);
236 case VecRegClass:
237 assert(vecMode == Enums::Full);
238 return vecMap.rename(arch_reg);
239 case VecElemClass:
240 assert(vecMode == Enums::Elem);
241 return vecElemMap.rename(arch_reg);
242 case VecPredRegClass:
243 return predMap.rename(arch_reg);
244 case CCRegClass:
245 return ccMap.rename(arch_reg);
246 case MiscRegClass:
247 {
248 // misc regs aren't really renamed, just remapped
249 PhysRegIdPtr phys_reg = lookup(arch_reg);
250 // Set the new register to the previous one to keep the same
251 // mapping throughout the execution.

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277 case VecRegClass:
278 assert(vecMode == Enums::Full);
279 return vecMap.lookup(arch_reg);
280
281 case VecElemClass:
282 assert(vecMode == Enums::Elem);
283 return vecElemMap.lookup(arch_reg);
284
285 case VecPredRegClass:
286 return predMap.lookup(arch_reg);
287
288 case CCRegClass:
289 return ccMap.lookup(arch_reg);
290
291 case MiscRegClass:
292 // misc regs aren't really renamed, they keep the same
293 // mapping throughout the execution.
294 return regFile->getMiscRegId(arch_reg.flatIndex());
295

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323 assert(vecMode == Enums::Full);
324 return vecMap.setEntry(arch_reg, phys_reg);
325
326 case VecElemClass:
327 assert(phys_reg->isVectorPhysElem());
328 assert(vecMode == Enums::Elem);
329 return vecElemMap.setEntry(arch_reg, phys_reg);
330
331 case VecPredRegClass:
332 assert(phys_reg->isVecPredPhysReg());
333 return predMap.setEntry(arch_reg, phys_reg);
334
335 case CCRegClass:
336 assert(phys_reg->isCCPhysReg());
337 return ccMap.setEntry(arch_reg, phys_reg);
338
339 case MiscRegClass:
340 // Misc registers do not actually rename, so don't change
341 // their mappings. We end up here when a commit or squash
342 // tries to update or undo a hardwired misc reg nmapping,

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353 /**
354 * Return the minimum number of free entries across all of the
355 * register classes. The minimum is used so we guarantee that
356 * this number of entries is available regardless of which class
357 * of registers is requested.
358 */
359 unsigned numFreeEntries() const
360 {
361 return std::min(std::min(
362 std::min(intMap.numFreeEntries(), floatMap.numFreeEntries()),
363 vecMode == Enums::Full ? vecMap.numFreeEntries()
364 : vecElemMap.numFreeEntries()),
365 predMap.numFreeEntries());
366 }
367
368 unsigned numFreeIntEntries() const { return intMap.numFreeEntries(); }
369 unsigned numFreeFloatEntries() const { return floatMap.numFreeEntries(); }
370 unsigned numFreeVecEntries() const
371 {
372 return vecMode == Enums::Full
373 ? vecMap.numFreeEntries()
374 : vecElemMap.numFreeEntries();
375 }
376 unsigned numFreePredEntries() const { return predMap.numFreeEntries(); }
377 unsigned numFreeCCEntries() const { return ccMap.numFreeEntries(); }
378
379 /**
380 * Return whether there are enough registers to serve the request.
381 */
382 bool canRename(uint32_t intRegs, uint32_t floatRegs, uint32_t vectorRegs,
383 uint32_t vecElemRegs, uint32_t vecPredRegs,
384 uint32_t ccRegs) const
385 {
386 return intRegs <= intMap.numFreeEntries() &&
387 floatRegs <= floatMap.numFreeEntries() &&
388 vectorRegs <= vecMap.numFreeEntries() &&
389 vecElemRegs <= vecElemMap.numFreeEntries() &&
390 vecPredRegs <= predMap.numFreeEntries() &&
391 ccRegs <= ccMap.numFreeEntries();
392 }
393 /**
394 * Set vector mode to Full or Elem.
395 * Ignore 'silent' modifications.
396 *
397 * @param newVecMode new vector renaming mode
398 */
399 void switchMode(VecMode newVecMode);
400
401 /**
402 * Switch freeList of registers from Full to Elem or vicevers
403 * depending on vecMode (vector renaming mode).
404 */
405 void switchFreeList(UnifiedFreeList* freeList);
406
407};
408
409#endif //__CPU_O3_RENAME_MAP_HH__