1/*
2 * Copyright (c) 2015-2016 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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60 * or floating point). Because the register class is implicitly
61 * determined by the rename map instance being accessed, all
62 * architectural register index parameters and values in this class
63 * are relative (e.g., %fp2 is just index 2).
64 */
65class SimpleRenameMap
66{
67 private:
68 using Arch2PhysMap = std::vector<PhysRegIdPtr>;
69 /** The acutal arch-to-phys register map */
70 Arch2PhysMap map;
71
72 /**
73 * Pointer to the free list from which new physical registers
74 * should be allocated in rename()
75 */
76 SimpleFreeList *freeList;
77
78 /**
79 * The architectural index of the zero register. This register is
80 * mapped but read-only, so we ignore attempts to rename it via
81 * the rename() method. If there is no such register for this map
82 * table, it should be set to an invalid index so that it never
83 * matches.
84 */
85 RegId zeroReg;
86
87 public:
88
89 SimpleRenameMap();
90
91 ~SimpleRenameMap() {};
92
93 /**

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107
108 /**
109 * Tell rename map to get a new free physical register to remap
110 * the specified architectural register.
111 * @param arch_reg The architectural register to remap.
112 * @return A RenameInfo pair indicating both the new and previous
113 * physical registers.
114 */
115 RenameInfo rename(const RegId& arch_reg);
116
117 /**
118 * Look up the physical register mapped to an architectural register.
119 * @param arch_reg The architectural register to look up.
120 * @return The physical register it is currently mapped to.
121 */
122 PhysRegIdPtr lookup(const RegId& arch_reg) const
123 {
124 assert(arch_reg.flatIndex() <= map.size());
125 return map[arch_reg.flatIndex()];
126 }
127
128 /**
129 * Update rename map with a specific mapping. Generally used to
130 * roll back to old mappings on a squash.
131 * @param arch_reg The architectural register to remap.
132 * @param phys_reg The physical register to remap it to.
133 */
134 void setEntry(const RegId& arch_reg, PhysRegIdPtr phys_reg)
135 {
136 assert(arch_reg.flatIndex() <= map.size());
137 map[arch_reg.flatIndex()] = phys_reg;
138 }
139
140 /** Return the number of free entries on the associated free list. */
141 unsigned numFreeEntries() const { return freeList->numFreeRegs(); }
142};
143
144
145/**

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182 void init(PhysRegFile *_regFile,
183 RegIndex _intZeroReg,
184 RegIndex _floatZeroReg,
185 UnifiedFreeList *freeList);
186
187 /**
188 * Tell rename map to get a new free physical register to remap
189 * the specified architectural register. This version takes a
190 * RegId and reads the appropriate class-specific rename table.
191 * @param arch_reg The architectural register id to remap.
192 * @return A RenameInfo pair indicating both the new and previous
193 * physical registers.
194 */
195 RenameInfo rename(const RegId& arch_reg)
196 {
197 switch (arch_reg.classValue()) {
198 case IntRegClass:
199 return intMap.rename(arch_reg);
200 case FloatRegClass:
201 return floatMap.rename(arch_reg);
202 case CCRegClass:
203 return ccMap.rename(arch_reg);
204 case MiscRegClass:
205 {
206 // misc regs aren't really renamed, just remapped
207 PhysRegIdPtr phys_reg = lookup(arch_reg);
208 // Set the new register to the previous one to keep the same
209 // mapping throughout the execution.
210 return RenameInfo(phys_reg, phys_reg);
211 }
212
213 default:
214 panic("rename rename(): unknown reg class %s\n",
215 arch_reg.className());
216 }
217 }
218
219 /**
220 * Look up the physical register mapped to an architectural register.
221 * This version takes a flattened architectural register id
222 * and calls the appropriate class-specific rename table.
223 * @param arch_reg The architectural register to look up.
224 * @return The physical register it is currently mapped to.
225 */
226 PhysRegIdPtr lookup(const RegId& arch_reg) const
227 {
228 switch (arch_reg.classValue()) {
229 case IntRegClass:
230 return intMap.lookup(arch_reg);
231
232 case FloatRegClass:
233 return floatMap.lookup(arch_reg);
234
235 case CCRegClass:
236 return ccMap.lookup(arch_reg);
237
238 case MiscRegClass:
239 // misc regs aren't really renamed, they keep the same
240 // mapping throughout the execution.
241 return regFile->getMiscRegId(arch_reg.flatIndex());
242
243 default:
244 panic("rename lookup(): unknown reg class %s\n",
245 arch_reg.className());
246 }
247 }
248
249 /**
250 * Update rename map with a specific mapping. Generally used to
251 * roll back to old mappings on a squash. This version takes a
252 * flattened architectural register id and calls the
253 * appropriate class-specific rename table.
254 * @param arch_reg The architectural register to remap.
255 * @param phys_reg The physical register to remap it to.
256 */
257 void setEntry(const RegId& arch_reg, PhysRegIdPtr phys_reg)
258 {
259 switch (arch_reg.classValue()) {
260 case IntRegClass:
261 assert(phys_reg->isIntPhysReg());
262 return intMap.setEntry(arch_reg, phys_reg);
263
264 case FloatRegClass:
265 assert(phys_reg->isFloatPhysReg());
266 return floatMap.setEntry(arch_reg, phys_reg);
267
268 case CCRegClass:
269 assert(phys_reg->isCCPhysReg());
270 return ccMap.setEntry(arch_reg, phys_reg);
271
272 case MiscRegClass:
273 // Misc registers do not actually rename, so don't change
274 // their mappings. We end up here when a commit or squash
275 // tries to update or undo a hardwired misc reg nmapping,
276 // which should always be setting it to what it already is.
277 assert(phys_reg == lookup(arch_reg));
278 return;
279
280 default:
281 panic("rename setEntry(): unknown reg class %s\n",
282 arch_reg.className());
283 }
284 }
285
286 /**
287 * Return the minimum number of free entries across all of the
288 * register classes. The minimum is used so we guarantee that
289 * this number of entries is available regardless of which class
290 * of registers is requested.
291 */

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