rename_map.cc (9919:803903a8dac1) | rename_map.cc (9920:028e4da64b42) |
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1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright --- 83 unchanged lines hidden (view full) --- 92 RegIndex _floatZeroReg, 93 UnifiedFreeList *freeList) 94{ 95 regFile = _regFile; 96 97 intMap.init(TheISA::NumIntRegs, &(freeList->intList), _intZeroReg); 98 99 floatMap.init(TheISA::NumFloatRegs, &(freeList->floatList), _floatZeroReg); | 1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright --- 83 unchanged lines hidden (view full) --- 92 RegIndex _floatZeroReg, 93 UnifiedFreeList *freeList) 94{ 95 regFile = _regFile; 96 97 intMap.init(TheISA::NumIntRegs, &(freeList->intList), _intZeroReg); 98 99 floatMap.init(TheISA::NumFloatRegs, &(freeList->floatList), _floatZeroReg); |
100 101 ccMap.init(TheISA::NumFloatRegs, &(freeList->ccList), (RegIndex)-1); |
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100} 101 102 103UnifiedRenameMap::RenameInfo 104UnifiedRenameMap::rename(RegIndex arch_reg) 105{ 106 RegIndex rel_arch_reg; 107 108 switch (regIdxToClass(arch_reg, &rel_arch_reg)) { 109 case IntRegClass: 110 return renameInt(rel_arch_reg); 111 112 case FloatRegClass: 113 return renameFloat(rel_arch_reg); 114 | 102} 103 104 105UnifiedRenameMap::RenameInfo 106UnifiedRenameMap::rename(RegIndex arch_reg) 107{ 108 RegIndex rel_arch_reg; 109 110 switch (regIdxToClass(arch_reg, &rel_arch_reg)) { 111 case IntRegClass: 112 return renameInt(rel_arch_reg); 113 114 case FloatRegClass: 115 return renameFloat(rel_arch_reg); 116 |
117 case CCRegClass: 118 return renameCC(rel_arch_reg); 119 |
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115 case MiscRegClass: 116 return renameMisc(rel_arch_reg); 117 118 default: 119 panic("rename rename(): unknown reg class %s\n", 120 RegClassStrings[regIdxToClass(arch_reg)]); 121 } 122} --- 6 unchanged lines hidden (view full) --- 129 130 switch (regIdxToClass(arch_reg, &rel_arch_reg)) { 131 case IntRegClass: 132 return lookupInt(rel_arch_reg); 133 134 case FloatRegClass: 135 return lookupFloat(rel_arch_reg); 136 | 120 case MiscRegClass: 121 return renameMisc(rel_arch_reg); 122 123 default: 124 panic("rename rename(): unknown reg class %s\n", 125 RegClassStrings[regIdxToClass(arch_reg)]); 126 } 127} --- 6 unchanged lines hidden (view full) --- 134 135 switch (regIdxToClass(arch_reg, &rel_arch_reg)) { 136 case IntRegClass: 137 return lookupInt(rel_arch_reg); 138 139 case FloatRegClass: 140 return lookupFloat(rel_arch_reg); 141 |
142 case CCRegClass: 143 return lookupCC(rel_arch_reg); 144 |
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137 case MiscRegClass: 138 return lookupMisc(rel_arch_reg); 139 140 default: 141 panic("rename lookup(): unknown reg class %s\n", 142 RegClassStrings[regIdxToClass(arch_reg)]); 143 } 144} --- 5 unchanged lines hidden (view full) --- 150 151 switch (regIdxToClass(arch_reg, &rel_arch_reg)) { 152 case IntRegClass: 153 return setIntEntry(rel_arch_reg, phys_reg); 154 155 case FloatRegClass: 156 return setFloatEntry(rel_arch_reg, phys_reg); 157 | 145 case MiscRegClass: 146 return lookupMisc(rel_arch_reg); 147 148 default: 149 panic("rename lookup(): unknown reg class %s\n", 150 RegClassStrings[regIdxToClass(arch_reg)]); 151 } 152} --- 5 unchanged lines hidden (view full) --- 158 159 switch (regIdxToClass(arch_reg, &rel_arch_reg)) { 160 case IntRegClass: 161 return setIntEntry(rel_arch_reg, phys_reg); 162 163 case FloatRegClass: 164 return setFloatEntry(rel_arch_reg, phys_reg); 165 |
166 case CCRegClass: 167 return setCCEntry(rel_arch_reg, phys_reg); 168 |
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158 case MiscRegClass: 159 // Misc registers do not actually rename, so don't change 160 // their mappings. We end up here when a commit or squash 161 // tries to update or undo a hardwired misc reg nmapping, 162 // which should always be setting it to what it already is. 163 assert(phys_reg == lookupMisc(rel_arch_reg)); 164 return; 165 166 default: 167 panic("rename setEntry(): unknown reg class %s\n", 168 RegClassStrings[regIdxToClass(arch_reg)]); 169 } 170} | 169 case MiscRegClass: 170 // Misc registers do not actually rename, so don't change 171 // their mappings. We end up here when a commit or squash 172 // tries to update or undo a hardwired misc reg nmapping, 173 // which should always be setting it to what it already is. 174 assert(phys_reg == lookupMisc(rel_arch_reg)); 175 return; 176 177 default: 178 panic("rename setEntry(): unknown reg class %s\n", 179 RegClassStrings[regIdxToClass(arch_reg)]); 180 } 181} |