rename_map.cc (4030:4046b2213995) rename_map.cc (4642:d7b2de2d72f1)
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 151 unchanged lines hidden (view full) ---

160 }
161 } else if (arch_reg < numLogicalRegs) {
162 // Record the current physical register that is renamed to the
163 // requested architected register.
164 prev_reg = floatRenameMap[arch_reg].physical_reg;
165
166 // If it's not referencing the zero register, then rename the
167 // register.
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 151 unchanged lines hidden (view full) ---

160 }
161 } else if (arch_reg < numLogicalRegs) {
162 // Record the current physical register that is renamed to the
163 // requested architected register.
164 prev_reg = floatRenameMap[arch_reg].physical_reg;
165
166 // If it's not referencing the zero register, then rename the
167 // register.
168#if THE_ISA == ALPHA_ISA
168 if (arch_reg != floatZeroReg) {
169 if (arch_reg != floatZeroReg) {
170#endif
169 renamed_reg = freeList->getFloatReg();
170
171 floatRenameMap[arch_reg].physical_reg = renamed_reg;
172
173 assert(renamed_reg < numPhysicalRegs &&
174 renamed_reg >= numPhysicalIntRegs);
171 renamed_reg = freeList->getFloatReg();
172
173 floatRenameMap[arch_reg].physical_reg = renamed_reg;
174
175 assert(renamed_reg < numPhysicalRegs &&
176 renamed_reg >= numPhysicalIntRegs);
177#if THE_ISA == ALPHA_ISA
175 } else {
176 // Otherwise return the zero register so nothing bad happens.
177 renamed_reg = floatZeroReg;
178 }
178 } else {
179 // Otherwise return the zero register so nothing bad happens.
180 renamed_reg = floatZeroReg;
181 }
182#endif
179 } else {
180 // Subtract off the base offset for miscellaneous registers.
181 arch_reg = arch_reg - numLogicalRegs;
182
183 DPRINTF(Rename, "Renamed misc reg %d\n", arch_reg);
184
185 // No renaming happens to the misc. registers. They are
186 // simply the registers that come after all the physical

--- 64 unchanged lines hidden --- 		183 } else {
184 // Subtract off the base offset for miscellaneous registers.
185 arch_reg = arch_reg - numLogicalRegs;
186
187 DPRINTF(Rename, "Renamed misc reg %d\n", arch_reg);
188
189 // No renaming happens to the misc. registers. They are
190 // simply the registers that come after all the physical

--- 64 unchanged lines hidden ---