rename_map.cc (12105:742d80361989) | rename_map.cc (12106:7784fac1b159) |
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1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright --- 19 unchanged lines hidden (view full) --- 28 * 29 * Authors: Kevin Lim 30 */ 31 32#include "cpu/o3/rename_map.hh" 33 34#include <vector> 35 | 1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright --- 19 unchanged lines hidden (view full) --- 28 * 29 * Authors: Kevin Lim 30 */ 31 32#include "cpu/o3/rename_map.hh" 33 34#include <vector> 35 |
36#include "cpu/reg_class_impl.hh" |
|
36#include "debug/Rename.hh" 37 38using namespace std; 39 40/**** SimpleRenameMap methods ****/ 41 42SimpleRenameMap::SimpleRenameMap() | 37#include "debug/Rename.hh" 38 39using namespace std; 40 41/**** SimpleRenameMap methods ****/ 42 43SimpleRenameMap::SimpleRenameMap() |
43 : freeList(NULL), zeroReg(0) | 44 : freeList(NULL), zeroReg(IntRegClass,0) |
44{ 45} 46 47 48void 49SimpleRenameMap::init(unsigned size, SimpleFreeList *_freeList, 50 RegIndex _zeroReg) 51{ 52 assert(freeList == NULL); 53 assert(map.empty()); 54 55 map.resize(size); 56 freeList = _freeList; | 45{ 46} 47 48 49void 50SimpleRenameMap::init(unsigned size, SimpleFreeList *_freeList, 51 RegIndex _zeroReg) 52{ 53 assert(freeList == NULL); 54 assert(map.empty()); 55 56 map.resize(size); 57 freeList = _freeList; |
57 zeroReg = _zeroReg; | 58 zeroReg = RegId(IntRegClass, _zeroReg); |
58} 59 60SimpleRenameMap::RenameInfo | 59} 60 61SimpleRenameMap::RenameInfo |
61SimpleRenameMap::rename(RegIndex arch_reg) | 62SimpleRenameMap::rename(const RegId& arch_reg) |
62{ 63 PhysRegIdPtr renamed_reg; | 63{ 64 PhysRegIdPtr renamed_reg; |
64 | |
65 // Record the current physical register that is renamed to the 66 // requested architected register. | 65 // Record the current physical register that is renamed to the 66 // requested architected register. |
67 PhysRegIdPtr prev_reg = map[arch_reg]; | 67 PhysRegIdPtr prev_reg = map[arch_reg.index()]; |
68 69 // If it's not referencing the zero register, then rename the 70 // register. 71 if (arch_reg != zeroReg) { 72 renamed_reg = freeList->getReg(); 73 | 68 69 // If it's not referencing the zero register, then rename the 70 // register. 71 if (arch_reg != zeroReg) { 72 renamed_reg = freeList->getReg(); 73 |
74 map[arch_reg] = renamed_reg; | 74 map[arch_reg.index()] = renamed_reg; |
75 } else { 76 // Otherwise return the zero register so nothing bad happens. 77 assert(prev_reg->isZeroReg()); 78 renamed_reg = prev_reg; 79 } 80 81 DPRINTF(Rename, "Renamed reg %d to physical reg %d (%d) old mapping was" 82 " %d (%d)\n", | 75 } else { 76 // Otherwise return the zero register so nothing bad happens. 77 assert(prev_reg->isZeroReg()); 78 renamed_reg = prev_reg; 79 } 80 81 DPRINTF(Rename, "Renamed reg %d to physical reg %d (%d) old mapping was" 82 " %d (%d)\n", |
83 arch_reg, renamed_reg->regIdx, renamed_reg->flatIdx, 84 prev_reg->regIdx, prev_reg->flatIdx); | 83 arch_reg, renamed_reg->index(), renamed_reg->flatIndex(), 84 prev_reg->index(), prev_reg->flatIndex()); |
85 86 return RenameInfo(renamed_reg, prev_reg); 87} 88 89 90/**** UnifiedRenameMap methods ****/ 91 92void --- 7 unchanged lines hidden (view full) --- 100 intMap.init(TheISA::NumIntRegs, &(freeList->intList), _intZeroReg); 101 102 floatMap.init(TheISA::NumFloatRegs, &(freeList->floatList), _floatZeroReg); 103 104 ccMap.init(TheISA::NumCCRegs, &(freeList->ccList), (RegIndex)-1); 105 106} 107 | 85 86 return RenameInfo(renamed_reg, prev_reg); 87} 88 89 90/**** UnifiedRenameMap methods ****/ 91 92void --- 7 unchanged lines hidden (view full) --- 100 intMap.init(TheISA::NumIntRegs, &(freeList->intList), _intZeroReg); 101 102 floatMap.init(TheISA::NumFloatRegs, &(freeList->floatList), _floatZeroReg); 103 104 ccMap.init(TheISA::NumCCRegs, &(freeList->ccList), (RegIndex)-1); 105 106} 107 |
108 109UnifiedRenameMap::RenameInfo 110UnifiedRenameMap::rename(RegId arch_reg) 111{ 112 switch (arch_reg.regClass) { 113 case IntRegClass: 114 return renameInt(arch_reg.regIdx); 115 116 case FloatRegClass: 117 return renameFloat(arch_reg.regIdx); 118 119 case CCRegClass: 120 return renameCC(arch_reg.regIdx); 121 122 case MiscRegClass: 123 return renameMisc(arch_reg.regIdx); 124 125 default: 126 panic("rename rename(): unknown reg class %s\n", 127 RegClassStrings[arch_reg.regClass]); 128 } 129} 130 131 132PhysRegIdPtr 133UnifiedRenameMap::lookup(RegId arch_reg) const 134{ 135 switch (arch_reg.regClass) { 136 case IntRegClass: 137 return lookupInt(arch_reg.regIdx); 138 139 case FloatRegClass: 140 return lookupFloat(arch_reg.regIdx); 141 142 case CCRegClass: 143 return lookupCC(arch_reg.regIdx); 144 145 case MiscRegClass: 146 return lookupMisc(arch_reg.regIdx); 147 148 default: 149 panic("rename lookup(): unknown reg class %s\n", 150 RegClassStrings[arch_reg.regClass]); 151 } 152} 153 154void 155UnifiedRenameMap::setEntry(RegId arch_reg, PhysRegIdPtr phys_reg) 156{ 157 switch (arch_reg.regClass) { 158 case IntRegClass: 159 return setIntEntry(arch_reg.regIdx, phys_reg); 160 161 case FloatRegClass: 162 return setFloatEntry(arch_reg.regIdx, phys_reg); 163 164 case CCRegClass: 165 return setCCEntry(arch_reg.regIdx, phys_reg); 166 167 case MiscRegClass: 168 // Misc registers do not actually rename, so don't change 169 // their mappings. We end up here when a commit or squash 170 // tries to update or undo a hardwired misc reg nmapping, 171 // which should always be setting it to what it already is. 172 assert(phys_reg == lookupMisc(arch_reg.regIdx)); 173 return; 174 175 default: 176 panic("rename setEntry(): unknown reg class %s\n", 177 RegClassStrings[arch_reg.regClass]); 178 } 179} | |