rename_map.cc (11793:ef606668d247) | rename_map.cc (12104:edd63f9c6184) |
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1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright --- 90 unchanged lines hidden (view full) --- 99 100 floatMap.init(TheISA::NumFloatRegs, &(freeList->floatList), _floatZeroReg); 101 102 ccMap.init(TheISA::NumCCRegs, &(freeList->ccList), (RegIndex)-1); 103} 104 105 106UnifiedRenameMap::RenameInfo | 1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright --- 90 unchanged lines hidden (view full) --- 99 100 floatMap.init(TheISA::NumFloatRegs, &(freeList->floatList), _floatZeroReg); 101 102 ccMap.init(TheISA::NumCCRegs, &(freeList->ccList), (RegIndex)-1); 103} 104 105 106UnifiedRenameMap::RenameInfo |
107UnifiedRenameMap::rename(RegIndex arch_reg) | 107UnifiedRenameMap::rename(RegId arch_reg) |
108{ | 108{ |
109 RegIndex rel_arch_reg; 110 111 switch (regIdxToClass(arch_reg, &rel_arch_reg)) { | 109 switch (arch_reg.regClass) { |
112 case IntRegClass: | 110 case IntRegClass: |
113 return renameInt(rel_arch_reg); | 111 return renameInt(arch_reg.regIdx); |
114 115 case FloatRegClass: | 112 113 case FloatRegClass: |
116 return renameFloat(rel_arch_reg); | 114 return renameFloat(arch_reg.regIdx); |
117 118 case CCRegClass: | 115 116 case CCRegClass: |
119 return renameCC(rel_arch_reg); | 117 return renameCC(arch_reg.regIdx); |
120 121 case MiscRegClass: | 118 119 case MiscRegClass: |
122 return renameMisc(rel_arch_reg); | 120 return renameMisc(arch_reg.regIdx); |
123 124 default: 125 panic("rename rename(): unknown reg class %s\n", | 121 122 default: 123 panic("rename rename(): unknown reg class %s\n", |
126 RegClassStrings[regIdxToClass(arch_reg)]); | 124 RegClassStrings[arch_reg.regClass]); |
127 } 128} 129 130 131PhysRegIndex | 125 } 126} 127 128 129PhysRegIndex |
132UnifiedRenameMap::lookup(RegIndex arch_reg) const | 130UnifiedRenameMap::lookup(RegId arch_reg) const |
133{ | 131{ |
134 RegIndex rel_arch_reg; 135 136 switch (regIdxToClass(arch_reg, &rel_arch_reg)) { | 132 switch (arch_reg.regClass) { |
137 case IntRegClass: | 133 case IntRegClass: |
138 return lookupInt(rel_arch_reg); | 134 return lookupInt(arch_reg.regIdx); |
139 140 case FloatRegClass: | 135 136 case FloatRegClass: |
141 return lookupFloat(rel_arch_reg); | 137 return lookupFloat(arch_reg.regIdx); |
142 143 case CCRegClass: | 138 139 case CCRegClass: |
144 return lookupCC(rel_arch_reg); | 140 return lookupCC(arch_reg.regIdx); |
145 146 case MiscRegClass: | 141 142 case MiscRegClass: |
147 return lookupMisc(rel_arch_reg); | 143 return lookupMisc(arch_reg.regIdx); |
148 149 default: 150 panic("rename lookup(): unknown reg class %s\n", | 144 145 default: 146 panic("rename lookup(): unknown reg class %s\n", |
151 RegClassStrings[regIdxToClass(arch_reg)]); | 147 RegClassStrings[arch_reg.regClass]); |
152 } 153} 154 155void | 148 } 149} 150 151void |
156UnifiedRenameMap::setEntry(RegIndex arch_reg, PhysRegIndex phys_reg) | 152UnifiedRenameMap::setEntry(RegId arch_reg, PhysRegIndex phys_reg) |
157{ | 153{ |
158 RegIndex rel_arch_reg; 159 160 switch (regIdxToClass(arch_reg, &rel_arch_reg)) { | 154 switch (arch_reg.regClass) { |
161 case IntRegClass: | 155 case IntRegClass: |
162 return setIntEntry(rel_arch_reg, phys_reg); | 156 return setIntEntry(arch_reg.regIdx, phys_reg); |
163 164 case FloatRegClass: | 157 158 case FloatRegClass: |
165 return setFloatEntry(rel_arch_reg, phys_reg); | 159 return setFloatEntry(arch_reg.regIdx, phys_reg); |
166 167 case CCRegClass: | 160 161 case CCRegClass: |
168 return setCCEntry(rel_arch_reg, phys_reg); | 162 return setCCEntry(arch_reg.regIdx, phys_reg); |
169 170 case MiscRegClass: 171 // Misc registers do not actually rename, so don't change 172 // their mappings. We end up here when a commit or squash 173 // tries to update or undo a hardwired misc reg nmapping, 174 // which should always be setting it to what it already is. | 163 164 case MiscRegClass: 165 // Misc registers do not actually rename, so don't change 166 // their mappings. We end up here when a commit or squash 167 // tries to update or undo a hardwired misc reg nmapping, 168 // which should always be setting it to what it already is. |
175 assert(phys_reg == lookupMisc(rel_arch_reg)); | 169 assert(phys_reg == lookupMisc(arch_reg.regIdx)); |
176 return; 177 178 default: 179 panic("rename setEntry(): unknown reg class %s\n", | 170 return; 171 172 default: 173 panic("rename setEntry(): unknown reg class %s\n", |
180 RegClassStrings[regIdxToClass(arch_reg)]); | 174 RegClassStrings[arch_reg.regClass]); |
181 } 182} | 175 } 176} |