rename_map.cc (10934:5af8f40d8f2c) rename_map.cc (10935:acd48ddd725f)
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

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94{
95 regFile = _regFile;
96
97 intMap.init(TheISA::NumIntRegs, &(freeList->intList), _intZeroReg);
98
99 floatMap.init(TheISA::NumFloatRegs, &(freeList->floatList), _floatZeroReg);
100
101 ccMap.init(TheISA::NumCCRegs, &(freeList->ccList), (RegIndex)-1);
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

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94{
95 regFile = _regFile;
96
97 intMap.init(TheISA::NumIntRegs, &(freeList->intList), _intZeroReg);
98
99 floatMap.init(TheISA::NumFloatRegs, &(freeList->floatList), _floatZeroReg);
100
101 ccMap.init(TheISA::NumCCRegs, &(freeList->ccList), (RegIndex)-1);
102
103 vectorMap.init(TheISA::NumVectorRegs, &(freeList->vectorList),
104 (RegIndex)-1);
105}
106
107
108UnifiedRenameMap::RenameInfo
109UnifiedRenameMap::rename(RegIndex arch_reg)
110{
111 RegIndex rel_arch_reg;
112
113 switch (regIdxToClass(arch_reg, &rel_arch_reg)) {
114 case IntRegClass:
115 return renameInt(rel_arch_reg);
116
117 case FloatRegClass:
118 return renameFloat(rel_arch_reg);
119
120 case CCRegClass:
121 return renameCC(rel_arch_reg);
122
102}
103
104
105UnifiedRenameMap::RenameInfo
106UnifiedRenameMap::rename(RegIndex arch_reg)
107{
108 RegIndex rel_arch_reg;
109
110 switch (regIdxToClass(arch_reg, &rel_arch_reg)) {
111 case IntRegClass:
112 return renameInt(rel_arch_reg);
113
114 case FloatRegClass:
115 return renameFloat(rel_arch_reg);
116
117 case CCRegClass:
118 return renameCC(rel_arch_reg);
119
123 case VectorRegClass:
124 return renameVector(rel_arch_reg);
125
126 case MiscRegClass:
127 return renameMisc(rel_arch_reg);
128
129 default:
130 panic("rename rename(): unknown reg class %s\n",
131 RegClassStrings[regIdxToClass(arch_reg)]);
132 }
133}

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143 return lookupInt(rel_arch_reg);
144
145 case FloatRegClass:
146 return lookupFloat(rel_arch_reg);
147
148 case CCRegClass:
149 return lookupCC(rel_arch_reg);
150
120 case MiscRegClass:
121 return renameMisc(rel_arch_reg);
122
123 default:
124 panic("rename rename(): unknown reg class %s\n",
125 RegClassStrings[regIdxToClass(arch_reg)]);
126 }
127}

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137 return lookupInt(rel_arch_reg);
138
139 case FloatRegClass:
140 return lookupFloat(rel_arch_reg);
141
142 case CCRegClass:
143 return lookupCC(rel_arch_reg);
144
151 case VectorRegClass:
152 return lookupVector(rel_arch_reg);
153
154 case MiscRegClass:
155 return lookupMisc(rel_arch_reg);
156
157 default:
158 panic("rename lookup(): unknown reg class %s\n",
159 RegClassStrings[regIdxToClass(arch_reg)]);
160 }
161}

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170 return setIntEntry(rel_arch_reg, phys_reg);
171
172 case FloatRegClass:
173 return setFloatEntry(rel_arch_reg, phys_reg);
174
175 case CCRegClass:
176 return setCCEntry(rel_arch_reg, phys_reg);
177
145 case MiscRegClass:
146 return lookupMisc(rel_arch_reg);
147
148 default:
149 panic("rename lookup(): unknown reg class %s\n",
150 RegClassStrings[regIdxToClass(arch_reg)]);
151 }
152}

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161 return setIntEntry(rel_arch_reg, phys_reg);
162
163 case FloatRegClass:
164 return setFloatEntry(rel_arch_reg, phys_reg);
165
166 case CCRegClass:
167 return setCCEntry(rel_arch_reg, phys_reg);
168
178 case VectorRegClass:
179 return setVectorEntry(rel_arch_reg, phys_reg);
180
181 case MiscRegClass:
182 // Misc registers do not actually rename, so don't change
183 // their mappings. We end up here when a commit or squash
184 // tries to update or undo a hardwired misc reg nmapping,
185 // which should always be setting it to what it already is.
186 assert(phys_reg == lookupMisc(rel_arch_reg));
187 return;
188
189 default:
190 panic("rename setEntry(): unknown reg class %s\n",
191 RegClassStrings[regIdxToClass(arch_reg)]);
192 }
193}
169 case MiscRegClass:
170 // Misc registers do not actually rename, so don't change
171 // their mappings. We end up here when a commit or squash
172 // tries to update or undo a hardwired misc reg nmapping,
173 // which should always be setting it to what it already is.
174 assert(phys_reg == lookupMisc(rel_arch_reg));
175 return;
176
177 default:
178 panic("rename setEntry(): unknown reg class %s\n",
179 RegClassStrings[regIdxToClass(arch_reg)]);
180 }
181}