1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
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3 * Copyright (c) 2013 Advanced Micro Devices, Inc. |
4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer; 10 * redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the
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31 32#include <vector> 33 34#include "cpu/o3/rename_map.hh" 35#include "debug/Rename.hh" 36 37using namespace std; 38
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38// @todo: Consider making inline bool functions that determine if the
39// register is a logical int, logical fp, physical int, physical fp,
40// etc.
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39/**** SimpleRenameMap methods ****/ |
40
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42SimpleRenameMap::~SimpleRenameMap()
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41SimpleRenameMap::SimpleRenameMap() 42 : freeList(NULL) |
43{ 44} 45
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46 |
47void
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47SimpleRenameMap::init(unsigned _numLogicalIntRegs,
48 unsigned _numPhysicalIntRegs,
49 PhysRegIndex &ireg_idx,
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48SimpleRenameMap::init(unsigned size, SimpleFreeList *_freeList, 49 RegIndex _zeroReg) 50{ 51 assert(freeList == NULL); 52 assert(map.empty()); |
53
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51 unsigned _numLogicalFloatRegs,
52 unsigned _numPhysicalFloatRegs,
53 PhysRegIndex &freg_idx,
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54 map.resize(size); 55 freeList = _freeList; 56 zeroReg = _zeroReg; 57} |
58
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55 unsigned _numMiscRegs,
56
57 RegIndex _intZeroReg,
58 RegIndex _floatZeroReg,
59
60 int map_id,
61 bool bindRegs)
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59SimpleRenameMap::RenameInfo 60SimpleRenameMap::rename(RegIndex arch_reg) |
61{
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63 id = map_id;
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62 PhysRegIndex renamed_reg; |
63
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65 numLogicalIntRegs = _numLogicalIntRegs;
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64 // Record the current physical register that is renamed to the 65 // requested architected register. 66 PhysRegIndex prev_reg = map[arch_reg]; |
67
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67 numLogicalFloatRegs = _numLogicalFloatRegs;
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68 // If it's not referencing the zero register, then rename the 69 // register. 70 if (arch_reg != zeroReg) { 71 renamed_reg = freeList->getReg(); |
72
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69 numPhysicalIntRegs = _numPhysicalIntRegs;
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73 map[arch_reg] = renamed_reg; 74 } else { 75 // Otherwise return the zero register so nothing bad happens. 76 assert(prev_reg == zeroReg); 77 renamed_reg = zeroReg; 78 } |
79
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71 numPhysicalFloatRegs = _numPhysicalFloatRegs;
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80 DPRINTF(Rename, "Renamed reg %d to physical reg %d old mapping was %d\n", 81 arch_reg, renamed_reg, prev_reg); |
82
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73 numMiscRegs = _numMiscRegs;
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83 return RenameInfo(renamed_reg, prev_reg); 84} |
85
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75 intZeroReg = _intZeroReg;
76 floatZeroReg = _floatZeroReg;
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86
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78 DPRINTF(Rename, "Creating rename map %i. Phys: %i / %i, Float: "
79 "%i / %i.\n", id, numLogicalIntRegs, numPhysicalIntRegs,
80 numLogicalFloatRegs, numPhysicalFloatRegs);
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87/**** UnifiedRenameMap methods ****/ |
88
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82 numLogicalRegs = numLogicalIntRegs + numLogicalFloatRegs;
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89void 90UnifiedRenameMap::init(PhysRegFile *_regFile, 91 RegIndex _intZeroReg, 92 RegIndex _floatZeroReg, 93 UnifiedFreeList *freeList) 94{ 95 regFile = _regFile; |
96
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84 numPhysicalRegs = numPhysicalIntRegs + numPhysicalFloatRegs;
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97 intMap.init(TheISA::NumIntRegs, &(freeList->intList), _intZeroReg); |
98
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86 //Create the rename maps
87 intRenameMap.resize(numLogicalIntRegs);
88 floatRenameMap.resize(numLogicalRegs);
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99 floatMap.init(TheISA::NumFloatRegs, &(freeList->floatList), _floatZeroReg); 100} |
101
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90 if (bindRegs) {
91 DPRINTF(Rename, "Binding registers into rename map %i\n",id);
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102
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93 // Initialize the entries in the integer rename map to point to the
94 // physical registers of the same index
95 for (RegIndex index = 0; index < numLogicalIntRegs; ++index)
96 {
97 intRenameMap[index].physical_reg = ireg_idx++;
98 }
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103UnifiedRenameMap::RenameInfo 104UnifiedRenameMap::rename(RegIndex arch_reg) 105{ 106 RegIndex rel_arch_reg; |
107
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100 // Initialize the entries in the floating point rename map to point to
101 // the physical registers of the same index
102 // Although the index refers purely to architected registers, because
103 // the floating reg indices come after the integer reg indices, they
104 // may exceed the size of a normal RegIndex (short).
105 for (PhysRegIndex index = numLogicalIntRegs;
106 index < numLogicalRegs; ++index)
107 {
108 floatRenameMap[index].physical_reg = freg_idx++;
109 }
110 } else {
111 DPRINTF(Rename, "Binding registers into rename map %i\n",id);
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108 switch (regIdxToClass(arch_reg, &rel_arch_reg)) { 109 case IntRegClass: 110 return renameInt(rel_arch_reg); |
111
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113 PhysRegIndex temp_ireg = ireg_idx;
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112 case FloatRegClass: 113 return renameFloat(rel_arch_reg); |
114
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115 for (RegIndex index = 0; index < numLogicalIntRegs; ++index)
116 {
117 intRenameMap[index].physical_reg = temp_ireg++;
118 }
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115 case MiscRegClass: 116 return renameMisc(rel_arch_reg); |
117
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120 PhysRegIndex temp_freg = freg_idx;
121
122 for (PhysRegIndex index = numLogicalIntRegs;
123 index < numLogicalRegs; ++index)
124 {
125 floatRenameMap[index].physical_reg = temp_freg++;
126 }
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118 default: 119 panic("rename rename(): unknown reg class %s\n", 120 RegClassStrings[regIdxToClass(arch_reg)]); |
121 } 122} 123
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130void
131SimpleRenameMap::setFreeList(SimpleFreeList *fl_ptr)
132{
133 freeList = fl_ptr;
134}
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124
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136
137SimpleRenameMap::RenameInfo
138SimpleRenameMap::rename(RegIndex arch_reg)
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125PhysRegIndex 126UnifiedRenameMap::lookup(RegIndex arch_reg) const |
127{
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140 PhysRegIndex renamed_reg;
141 PhysRegIndex prev_reg;
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128 RegIndex rel_arch_reg; |
129
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143 if (arch_reg < numLogicalIntRegs) {
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130 switch (regIdxToClass(arch_reg, &rel_arch_reg)) { 131 case IntRegClass: 132 return lookupInt(rel_arch_reg); |
133
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145 // Record the current physical register that is renamed to the
146 // requested architected register.
147 prev_reg = intRenameMap[arch_reg].physical_reg;
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134 case FloatRegClass: 135 return lookupFloat(rel_arch_reg); |
136
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149 // If it's not referencing the zero register, then rename the
150 // register.
151 if (arch_reg != intZeroReg) {
152 renamed_reg = freeList->getIntReg();
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137 case MiscRegClass: 138 return lookupMisc(rel_arch_reg); |
139
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154 intRenameMap[arch_reg].physical_reg = renamed_reg;
155
156 assert(renamed_reg >= 0 && renamed_reg < numPhysicalIntRegs);
157
158 } else {
159 // Otherwise return the zero register so nothing bad happens.
160 renamed_reg = intZeroReg;
161 prev_reg = intZeroReg;
162 }
163 } else if (arch_reg < numLogicalRegs) {
164 // Record the current physical register that is renamed to the
165 // requested architected register.
166 prev_reg = floatRenameMap[arch_reg].physical_reg;
167
168 // If it's not referencing the zero register, then rename the
169 // register.
170#if THE_ISA == ALPHA_ISA
171 if (arch_reg != floatZeroReg) {
172#endif
173 renamed_reg = freeList->getFloatReg();
174
175 floatRenameMap[arch_reg].physical_reg = renamed_reg;
176
177 assert(renamed_reg < numPhysicalRegs &&
178 renamed_reg >= numPhysicalIntRegs);
179#if THE_ISA == ALPHA_ISA
180 } else {
181 // Otherwise return the zero register so nothing bad happens.
182 renamed_reg = floatZeroReg;
183 }
184#endif
185 } else {
186 // Subtract off the base offset for miscellaneous registers.
187 arch_reg = arch_reg - numLogicalRegs;
188
189 DPRINTF(Rename, "Renamed misc reg %d\n", arch_reg);
190
191 // No renaming happens to the misc. registers. They are
192 // simply the registers that come after all the physical
193 // registers; thus take the base architected register and add
194 // the physical registers to it.
195 renamed_reg = arch_reg + numPhysicalRegs;
196
197 // Set the previous register to the same register; mainly it must be
198 // known that the prev reg was outside the range of normal registers
199 // so the free list can avoid adding it.
200 prev_reg = renamed_reg;
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140 default: 141 panic("rename lookup(): unknown reg class %s\n", 142 RegClassStrings[regIdxToClass(arch_reg)]); |
143 }
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202
203 DPRINTF(Rename, "Renamed reg %d to physical reg %d old mapping was %d\n",
204 arch_reg, renamed_reg, prev_reg);
205
206 return RenameInfo(renamed_reg, prev_reg);
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144} 145
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209PhysRegIndex
210SimpleRenameMap::lookup(RegIndex arch_reg)
211{
212 if (arch_reg < numLogicalIntRegs) {
213 return intRenameMap[arch_reg].physical_reg;
214 } else if (arch_reg < numLogicalRegs) {
215 return floatRenameMap[arch_reg].physical_reg;
216 } else {
217 // Subtract off the misc registers offset.
218 arch_reg = arch_reg - numLogicalRegs;
219
220 // Misc. regs don't rename, so simply add the base arch reg to
221 // the number of physical registers.
222 return numPhysicalRegs + arch_reg;
223 }
224}
225
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146void
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227SimpleRenameMap::setEntry(RegIndex arch_reg, PhysRegIndex renamed_reg)
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147UnifiedRenameMap::setEntry(RegIndex arch_reg, PhysRegIndex phys_reg) |
148{
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229 // In this implementation the miscellaneous registers do not
230 // actually rename, so this function does not allow you to try to
231 // change their mappings.
232 if (arch_reg < numLogicalIntRegs) {
233 DPRINTF(Rename, "Rename Map: Integer register %i being set to %i.\n",
234 (int)arch_reg, renamed_reg);
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149 RegIndex rel_arch_reg; |
150
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236 intRenameMap[arch_reg].physical_reg = renamed_reg;
237 } else if (arch_reg < numLogicalIntRegs + numLogicalFloatRegs) {
238 DPRINTF(Rename, "Rename Map: Float register %i being set to %i.\n",
239 (int)arch_reg - numLogicalIntRegs, renamed_reg);
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151 switch (regIdxToClass(arch_reg, &rel_arch_reg)) { 152 case IntRegClass: 153 return setIntEntry(rel_arch_reg, phys_reg); |
154
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241 floatRenameMap[arch_reg].physical_reg = renamed_reg;
242 }
243}
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155 case FloatRegClass: 156 return setFloatEntry(rel_arch_reg, phys_reg); |
157
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245int
246SimpleRenameMap::numFreeEntries()
247{
248 int free_int_regs = freeList->numFreeIntRegs();
249 int free_float_regs = freeList->numFreeFloatRegs();
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158 case MiscRegClass: 159 // Misc registers do not actually rename, so don't change 160 // their mappings. We end up here when a commit or squash 161 // tries to update or undo a hardwired misc reg nmapping, 162 // which should always be setting it to what it already is. 163 assert(phys_reg == lookupMisc(rel_arch_reg)); 164 return; |
165
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251 if (free_int_regs < free_float_regs) {
252 return free_int_regs;
253 } else {
254 return free_float_regs;
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166 default: 167 panic("rename setEntry(): unknown reg class %s\n", 168 RegClassStrings[regIdxToClass(arch_reg)]); |
169 } 170}
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