1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright --- 19 unchanged lines hidden (view full) --- 28 * 29 * Authors: Kevin Lim 30 */ 31 32#include "cpu/o3/rename_map.hh" 33 34#include <vector> 35 |
36#include "cpu/reg_class_impl.hh" |
37#include "debug/Rename.hh" 38 39using namespace std; 40 41/**** SimpleRenameMap methods ****/ 42 43SimpleRenameMap::SimpleRenameMap() |
44 : freeList(NULL), zeroReg(IntRegClass,0) |
45{ 46} 47 48 49void 50SimpleRenameMap::init(unsigned size, SimpleFreeList *_freeList, 51 RegIndex _zeroReg) 52{ 53 assert(freeList == NULL); 54 assert(map.empty()); 55 56 map.resize(size); 57 freeList = _freeList; |
58 zeroReg = RegId(IntRegClass, _zeroReg); |
59} 60 61SimpleRenameMap::RenameInfo |
62SimpleRenameMap::rename(const RegId& arch_reg) |
63{ 64 PhysRegIdPtr renamed_reg; |
65 // Record the current physical register that is renamed to the 66 // requested architected register. |
67 PhysRegIdPtr prev_reg = map[arch_reg.index()]; |
68 69 // If it's not referencing the zero register, then rename the 70 // register. 71 if (arch_reg != zeroReg) { 72 renamed_reg = freeList->getReg(); 73 |
74 map[arch_reg.index()] = renamed_reg; |
75 } else { 76 // Otherwise return the zero register so nothing bad happens. 77 assert(prev_reg->isZeroReg()); 78 renamed_reg = prev_reg; 79 } 80 81 DPRINTF(Rename, "Renamed reg %d to physical reg %d (%d) old mapping was" 82 " %d (%d)\n", |
83 arch_reg, renamed_reg->index(), renamed_reg->flatIndex(), 84 prev_reg->index(), prev_reg->flatIndex()); |
85 86 return RenameInfo(renamed_reg, prev_reg); 87} 88 89 90/**** UnifiedRenameMap methods ****/ 91 92void --- 7 unchanged lines hidden (view full) --- 100 intMap.init(TheISA::NumIntRegs, &(freeList->intList), _intZeroReg); 101 102 floatMap.init(TheISA::NumFloatRegs, &(freeList->floatList), _floatZeroReg); 103 104 ccMap.init(TheISA::NumCCRegs, &(freeList->ccList), (RegIndex)-1); 105 106} 107 |