2a3
> * Copyright (c) 2013 Advanced Micro Devices, Inc.
38,40c39
< // @todo: Consider making inline bool functions that determine if the
< // register is a logical int, logical fp, physical int, physical fp,
< // etc.
---
> /**** SimpleRenameMap methods ****/
42c41,42
< SimpleRenameMap::~SimpleRenameMap()
---
> SimpleRenameMap::SimpleRenameMap()
> : freeList(NULL)
45a46
>
47,49c48,52
< SimpleRenameMap::init(unsigned _numLogicalIntRegs,
< unsigned _numPhysicalIntRegs,
< PhysRegIndex &ireg_idx,
---
> SimpleRenameMap::init(unsigned size, SimpleFreeList *_freeList,
> RegIndex _zeroReg)
> {
> assert(freeList == NULL);
> assert(map.empty());
51,53c54,57
< unsigned _numLogicalFloatRegs,
< unsigned _numPhysicalFloatRegs,
< PhysRegIndex &freg_idx,
---
> map.resize(size);
> freeList = _freeList;
> zeroReg = _zeroReg;
> }
55,61c59,60
< unsigned _numMiscRegs,
<
< RegIndex _intZeroReg,
< RegIndex _floatZeroReg,
<
< int map_id,
< bool bindRegs)
---
> SimpleRenameMap::RenameInfo
> SimpleRenameMap::rename(RegIndex arch_reg)
63c62
< id = map_id;
---
> PhysRegIndex renamed_reg;
65c64,66
< numLogicalIntRegs = _numLogicalIntRegs;
---
> // Record the current physical register that is renamed to the
> // requested architected register.
> PhysRegIndex prev_reg = map[arch_reg];
67c68,71
< numLogicalFloatRegs = _numLogicalFloatRegs;
---
> // If it's not referencing the zero register, then rename the
> // register.
> if (arch_reg != zeroReg) {
> renamed_reg = freeList->getReg();
69c73,78
< numPhysicalIntRegs = _numPhysicalIntRegs;
---
> map[arch_reg] = renamed_reg;
> } else {
> // Otherwise return the zero register so nothing bad happens.
> assert(prev_reg == zeroReg);
> renamed_reg = zeroReg;
> }
71c80,81
< numPhysicalFloatRegs = _numPhysicalFloatRegs;
---
> DPRINTF(Rename, "Renamed reg %d to physical reg %d old mapping was %d\n",
> arch_reg, renamed_reg, prev_reg);
73c83,84
< numMiscRegs = _numMiscRegs;
---
> return RenameInfo(renamed_reg, prev_reg);
> }
75,76d85
< intZeroReg = _intZeroReg;
< floatZeroReg = _floatZeroReg;
78,80c87
< DPRINTF(Rename, "Creating rename map %i. Phys: %i / %i, Float: "
< "%i / %i.\n", id, numLogicalIntRegs, numPhysicalIntRegs,
< numLogicalFloatRegs, numPhysicalFloatRegs);
---
> /**** UnifiedRenameMap methods ****/
82c89,95
< numLogicalRegs = numLogicalIntRegs + numLogicalFloatRegs;
---
> void
> UnifiedRenameMap::init(PhysRegFile *_regFile,
> RegIndex _intZeroReg,
> RegIndex _floatZeroReg,
> UnifiedFreeList *freeList)
> {
> regFile = _regFile;
84c97
< numPhysicalRegs = numPhysicalIntRegs + numPhysicalFloatRegs;
---
> intMap.init(TheISA::NumIntRegs, &(freeList->intList), _intZeroReg);
86,88c99,100
< //Create the rename maps
< intRenameMap.resize(numLogicalIntRegs);
< floatRenameMap.resize(numLogicalRegs);
---
> floatMap.init(TheISA::NumFloatRegs, &(freeList->floatList), _floatZeroReg);
> }
90,91d101
< if (bindRegs) {
< DPRINTF(Rename, "Binding registers into rename map %i\n",id);
93,98c103,106
< // Initialize the entries in the integer rename map to point to the
< // physical registers of the same index
< for (RegIndex index = 0; index < numLogicalIntRegs; ++index)
< {
< intRenameMap[index].physical_reg = ireg_idx++;
< }
---
> UnifiedRenameMap::RenameInfo
> UnifiedRenameMap::rename(RegIndex arch_reg)
> {
> RegIndex rel_arch_reg;
100,111c108,110
< // Initialize the entries in the floating point rename map to point to
< // the physical registers of the same index
< // Although the index refers purely to architected registers, because
< // the floating reg indices come after the integer reg indices, they
< // may exceed the size of a normal RegIndex (short).
< for (PhysRegIndex index = numLogicalIntRegs;
< index < numLogicalRegs; ++index)
< {
< floatRenameMap[index].physical_reg = freg_idx++;
< }
< } else {
< DPRINTF(Rename, "Binding registers into rename map %i\n",id);
---
> switch (regIdxToClass(arch_reg, &rel_arch_reg)) {
> case IntRegClass:
> return renameInt(rel_arch_reg);
113c112,113
< PhysRegIndex temp_ireg = ireg_idx;
---
> case FloatRegClass:
> return renameFloat(rel_arch_reg);
115,118c115,116
< for (RegIndex index = 0; index < numLogicalIntRegs; ++index)
< {
< intRenameMap[index].physical_reg = temp_ireg++;
< }
---
> case MiscRegClass:
> return renameMisc(rel_arch_reg);
120,126c118,120
< PhysRegIndex temp_freg = freg_idx;
<
< for (PhysRegIndex index = numLogicalIntRegs;
< index < numLogicalRegs; ++index)
< {
< floatRenameMap[index].physical_reg = temp_freg++;
< }
---
> default:
> panic("rename rename(): unknown reg class %s\n",
> RegClassStrings[regIdxToClass(arch_reg)]);
130,134d123
< void
< SimpleRenameMap::setFreeList(SimpleFreeList *fl_ptr)
< {
< freeList = fl_ptr;
< }
136,138c125,126
<
< SimpleRenameMap::RenameInfo
< SimpleRenameMap::rename(RegIndex arch_reg)
---
> PhysRegIndex
> UnifiedRenameMap::lookup(RegIndex arch_reg) const
140,141c128
< PhysRegIndex renamed_reg;
< PhysRegIndex prev_reg;
---
> RegIndex rel_arch_reg;
143c130,132
< if (arch_reg < numLogicalIntRegs) {
---
> switch (regIdxToClass(arch_reg, &rel_arch_reg)) {
> case IntRegClass:
> return lookupInt(rel_arch_reg);
145,147c134,135
< // Record the current physical register that is renamed to the
< // requested architected register.
< prev_reg = intRenameMap[arch_reg].physical_reg;
---
> case FloatRegClass:
> return lookupFloat(rel_arch_reg);
149,152c137,138
< // If it's not referencing the zero register, then rename the
< // register.
< if (arch_reg != intZeroReg) {
< renamed_reg = freeList->getIntReg();
---
> case MiscRegClass:
> return lookupMisc(rel_arch_reg);
154,200c140,142
< intRenameMap[arch_reg].physical_reg = renamed_reg;
<
< assert(renamed_reg >= 0 && renamed_reg < numPhysicalIntRegs);
<
< } else {
< // Otherwise return the zero register so nothing bad happens.
< renamed_reg = intZeroReg;
< prev_reg = intZeroReg;
< }
< } else if (arch_reg < numLogicalRegs) {
< // Record the current physical register that is renamed to the
< // requested architected register.
< prev_reg = floatRenameMap[arch_reg].physical_reg;
<
< // If it's not referencing the zero register, then rename the
< // register.
< #if THE_ISA == ALPHA_ISA
< if (arch_reg != floatZeroReg) {
< #endif
< renamed_reg = freeList->getFloatReg();
<
< floatRenameMap[arch_reg].physical_reg = renamed_reg;
<
< assert(renamed_reg < numPhysicalRegs &&
< renamed_reg >= numPhysicalIntRegs);
< #if THE_ISA == ALPHA_ISA
< } else {
< // Otherwise return the zero register so nothing bad happens.
< renamed_reg = floatZeroReg;
< }
< #endif
< } else {
< // Subtract off the base offset for miscellaneous registers.
< arch_reg = arch_reg - numLogicalRegs;
<
< DPRINTF(Rename, "Renamed misc reg %d\n", arch_reg);
<
< // No renaming happens to the misc. registers. They are
< // simply the registers that come after all the physical
< // registers; thus take the base architected register and add
< // the physical registers to it.
< renamed_reg = arch_reg + numPhysicalRegs;
<
< // Set the previous register to the same register; mainly it must be
< // known that the prev reg was outside the range of normal registers
< // so the free list can avoid adding it.
< prev_reg = renamed_reg;
---
> default:
> panic("rename lookup(): unknown reg class %s\n",
> RegClassStrings[regIdxToClass(arch_reg)]);
202,206d143
<
< DPRINTF(Rename, "Renamed reg %d to physical reg %d old mapping was %d\n",
< arch_reg, renamed_reg, prev_reg);
<
< return RenameInfo(renamed_reg, prev_reg);
209,225d145
< PhysRegIndex
< SimpleRenameMap::lookup(RegIndex arch_reg)
< {
< if (arch_reg < numLogicalIntRegs) {
< return intRenameMap[arch_reg].physical_reg;
< } else if (arch_reg < numLogicalRegs) {
< return floatRenameMap[arch_reg].physical_reg;
< } else {
< // Subtract off the misc registers offset.
< arch_reg = arch_reg - numLogicalRegs;
<
< // Misc. regs don't rename, so simply add the base arch reg to
< // the number of physical registers.
< return numPhysicalRegs + arch_reg;
< }
< }
<
227c147
< SimpleRenameMap::setEntry(RegIndex arch_reg, PhysRegIndex renamed_reg)
---
> UnifiedRenameMap::setEntry(RegIndex arch_reg, PhysRegIndex phys_reg)
229,234c149
< // In this implementation the miscellaneous registers do not
< // actually rename, so this function does not allow you to try to
< // change their mappings.
< if (arch_reg < numLogicalIntRegs) {
< DPRINTF(Rename, "Rename Map: Integer register %i being set to %i.\n",
< (int)arch_reg, renamed_reg);
---
> RegIndex rel_arch_reg;
236,239c151,153
< intRenameMap[arch_reg].physical_reg = renamed_reg;
< } else if (arch_reg < numLogicalIntRegs + numLogicalFloatRegs) {
< DPRINTF(Rename, "Rename Map: Float register %i being set to %i.\n",
< (int)arch_reg - numLogicalIntRegs, renamed_reg);
---
> switch (regIdxToClass(arch_reg, &rel_arch_reg)) {
> case IntRegClass:
> return setIntEntry(rel_arch_reg, phys_reg);
241,243c155,156
< floatRenameMap[arch_reg].physical_reg = renamed_reg;
< }
< }
---
> case FloatRegClass:
> return setFloatEntry(rel_arch_reg, phys_reg);
245,249c158,164
< int
< SimpleRenameMap::numFreeEntries()
< {
< int free_int_regs = freeList->numFreeIntRegs();
< int free_float_regs = freeList->numFreeFloatRegs();
---
> case MiscRegClass:
> // Misc registers do not actually rename, so don't change
> // their mappings. We end up here when a commit or squash
> // tries to update or undo a hardwired misc reg nmapping,
> // which should always be setting it to what it already is.
> assert(phys_reg == lookupMisc(rel_arch_reg));
> return;
251,254c166,168
< if (free_int_regs < free_float_regs) {
< return free_int_regs;
< } else {
< return free_float_regs;
---
> default:
> panic("rename setEntry(): unknown reg class %s\n",
> RegClassStrings[regIdxToClass(arch_reg)]);
> * Copyright (c) 2013 Advanced Micro Devices, Inc.
38,40c39
< // @todo: Consider making inline bool functions that determine if the
< // register is a logical int, logical fp, physical int, physical fp,
< // etc.
---
> /**** SimpleRenameMap methods ****/
42c41,42
< SimpleRenameMap::~SimpleRenameMap()
---
> SimpleRenameMap::SimpleRenameMap()
> : freeList(NULL)
45a46
>
47,49c48,52
< SimpleRenameMap::init(unsigned _numLogicalIntRegs,
< unsigned _numPhysicalIntRegs,
< PhysRegIndex &ireg_idx,
---
> SimpleRenameMap::init(unsigned size, SimpleFreeList *_freeList,
> RegIndex _zeroReg)
> {
> assert(freeList == NULL);
> assert(map.empty());
51,53c54,57
< unsigned _numLogicalFloatRegs,
< unsigned _numPhysicalFloatRegs,
< PhysRegIndex &freg_idx,
---
> map.resize(size);
> freeList = _freeList;
> zeroReg = _zeroReg;
> }
55,61c59,60
< unsigned _numMiscRegs,
<
< RegIndex _intZeroReg,
< RegIndex _floatZeroReg,
<
< int map_id,
< bool bindRegs)
---
> SimpleRenameMap::RenameInfo
> SimpleRenameMap::rename(RegIndex arch_reg)
63c62
< id = map_id;
---
> PhysRegIndex renamed_reg;
65c64,66
< numLogicalIntRegs = _numLogicalIntRegs;
---
> // Record the current physical register that is renamed to the
> // requested architected register.
> PhysRegIndex prev_reg = map[arch_reg];
67c68,71
< numLogicalFloatRegs = _numLogicalFloatRegs;
---
> // If it's not referencing the zero register, then rename the
> // register.
> if (arch_reg != zeroReg) {
> renamed_reg = freeList->getReg();
69c73,78
< numPhysicalIntRegs = _numPhysicalIntRegs;
---
> map[arch_reg] = renamed_reg;
> } else {
> // Otherwise return the zero register so nothing bad happens.
> assert(prev_reg == zeroReg);
> renamed_reg = zeroReg;
> }
71c80,81
< numPhysicalFloatRegs = _numPhysicalFloatRegs;
---
> DPRINTF(Rename, "Renamed reg %d to physical reg %d old mapping was %d\n",
> arch_reg, renamed_reg, prev_reg);
73c83,84
< numMiscRegs = _numMiscRegs;
---
> return RenameInfo(renamed_reg, prev_reg);
> }
75,76d85
< intZeroReg = _intZeroReg;
< floatZeroReg = _floatZeroReg;
78,80c87
< DPRINTF(Rename, "Creating rename map %i. Phys: %i / %i, Float: "
< "%i / %i.\n", id, numLogicalIntRegs, numPhysicalIntRegs,
< numLogicalFloatRegs, numPhysicalFloatRegs);
---
> /**** UnifiedRenameMap methods ****/
82c89,95
< numLogicalRegs = numLogicalIntRegs + numLogicalFloatRegs;
---
> void
> UnifiedRenameMap::init(PhysRegFile *_regFile,
> RegIndex _intZeroReg,
> RegIndex _floatZeroReg,
> UnifiedFreeList *freeList)
> {
> regFile = _regFile;
84c97
< numPhysicalRegs = numPhysicalIntRegs + numPhysicalFloatRegs;
---
> intMap.init(TheISA::NumIntRegs, &(freeList->intList), _intZeroReg);
86,88c99,100
< //Create the rename maps
< intRenameMap.resize(numLogicalIntRegs);
< floatRenameMap.resize(numLogicalRegs);
---
> floatMap.init(TheISA::NumFloatRegs, &(freeList->floatList), _floatZeroReg);
> }
90,91d101
< if (bindRegs) {
< DPRINTF(Rename, "Binding registers into rename map %i\n",id);
93,98c103,106
< // Initialize the entries in the integer rename map to point to the
< // physical registers of the same index
< for (RegIndex index = 0; index < numLogicalIntRegs; ++index)
< {
< intRenameMap[index].physical_reg = ireg_idx++;
< }
---
> UnifiedRenameMap::RenameInfo
> UnifiedRenameMap::rename(RegIndex arch_reg)
> {
> RegIndex rel_arch_reg;
100,111c108,110
< // Initialize the entries in the floating point rename map to point to
< // the physical registers of the same index
< // Although the index refers purely to architected registers, because
< // the floating reg indices come after the integer reg indices, they
< // may exceed the size of a normal RegIndex (short).
< for (PhysRegIndex index = numLogicalIntRegs;
< index < numLogicalRegs; ++index)
< {
< floatRenameMap[index].physical_reg = freg_idx++;
< }
< } else {
< DPRINTF(Rename, "Binding registers into rename map %i\n",id);
---
> switch (regIdxToClass(arch_reg, &rel_arch_reg)) {
> case IntRegClass:
> return renameInt(rel_arch_reg);
113c112,113
< PhysRegIndex temp_ireg = ireg_idx;
---
> case FloatRegClass:
> return renameFloat(rel_arch_reg);
115,118c115,116
< for (RegIndex index = 0; index < numLogicalIntRegs; ++index)
< {
< intRenameMap[index].physical_reg = temp_ireg++;
< }
---
> case MiscRegClass:
> return renameMisc(rel_arch_reg);
120,126c118,120
< PhysRegIndex temp_freg = freg_idx;
<
< for (PhysRegIndex index = numLogicalIntRegs;
< index < numLogicalRegs; ++index)
< {
< floatRenameMap[index].physical_reg = temp_freg++;
< }
---
> default:
> panic("rename rename(): unknown reg class %s\n",
> RegClassStrings[regIdxToClass(arch_reg)]);
130,134d123
< void
< SimpleRenameMap::setFreeList(SimpleFreeList *fl_ptr)
< {
< freeList = fl_ptr;
< }
136,138c125,126
<
< SimpleRenameMap::RenameInfo
< SimpleRenameMap::rename(RegIndex arch_reg)
---
> PhysRegIndex
> UnifiedRenameMap::lookup(RegIndex arch_reg) const
140,141c128
< PhysRegIndex renamed_reg;
< PhysRegIndex prev_reg;
---
> RegIndex rel_arch_reg;
143c130,132
< if (arch_reg < numLogicalIntRegs) {
---
> switch (regIdxToClass(arch_reg, &rel_arch_reg)) {
> case IntRegClass:
> return lookupInt(rel_arch_reg);
145,147c134,135
< // Record the current physical register that is renamed to the
< // requested architected register.
< prev_reg = intRenameMap[arch_reg].physical_reg;
---
> case FloatRegClass:
> return lookupFloat(rel_arch_reg);
149,152c137,138
< // If it's not referencing the zero register, then rename the
< // register.
< if (arch_reg != intZeroReg) {
< renamed_reg = freeList->getIntReg();
---
> case MiscRegClass:
> return lookupMisc(rel_arch_reg);
154,200c140,142
< intRenameMap[arch_reg].physical_reg = renamed_reg;
<
< assert(renamed_reg >= 0 && renamed_reg < numPhysicalIntRegs);
<
< } else {
< // Otherwise return the zero register so nothing bad happens.
< renamed_reg = intZeroReg;
< prev_reg = intZeroReg;
< }
< } else if (arch_reg < numLogicalRegs) {
< // Record the current physical register that is renamed to the
< // requested architected register.
< prev_reg = floatRenameMap[arch_reg].physical_reg;
<
< // If it's not referencing the zero register, then rename the
< // register.
< #if THE_ISA == ALPHA_ISA
< if (arch_reg != floatZeroReg) {
< #endif
< renamed_reg = freeList->getFloatReg();
<
< floatRenameMap[arch_reg].physical_reg = renamed_reg;
<
< assert(renamed_reg < numPhysicalRegs &&
< renamed_reg >= numPhysicalIntRegs);
< #if THE_ISA == ALPHA_ISA
< } else {
< // Otherwise return the zero register so nothing bad happens.
< renamed_reg = floatZeroReg;
< }
< #endif
< } else {
< // Subtract off the base offset for miscellaneous registers.
< arch_reg = arch_reg - numLogicalRegs;
<
< DPRINTF(Rename, "Renamed misc reg %d\n", arch_reg);
<
< // No renaming happens to the misc. registers. They are
< // simply the registers that come after all the physical
< // registers; thus take the base architected register and add
< // the physical registers to it.
< renamed_reg = arch_reg + numPhysicalRegs;
<
< // Set the previous register to the same register; mainly it must be
< // known that the prev reg was outside the range of normal registers
< // so the free list can avoid adding it.
< prev_reg = renamed_reg;
---
> default:
> panic("rename lookup(): unknown reg class %s\n",
> RegClassStrings[regIdxToClass(arch_reg)]);
202,206d143
<
< DPRINTF(Rename, "Renamed reg %d to physical reg %d old mapping was %d\n",
< arch_reg, renamed_reg, prev_reg);
<
< return RenameInfo(renamed_reg, prev_reg);
209,225d145
< PhysRegIndex
< SimpleRenameMap::lookup(RegIndex arch_reg)
< {
< if (arch_reg < numLogicalIntRegs) {
< return intRenameMap[arch_reg].physical_reg;
< } else if (arch_reg < numLogicalRegs) {
< return floatRenameMap[arch_reg].physical_reg;
< } else {
< // Subtract off the misc registers offset.
< arch_reg = arch_reg - numLogicalRegs;
<
< // Misc. regs don't rename, so simply add the base arch reg to
< // the number of physical registers.
< return numPhysicalRegs + arch_reg;
< }
< }
<
227c147
< SimpleRenameMap::setEntry(RegIndex arch_reg, PhysRegIndex renamed_reg)
---
> UnifiedRenameMap::setEntry(RegIndex arch_reg, PhysRegIndex phys_reg)
229,234c149
< // In this implementation the miscellaneous registers do not
< // actually rename, so this function does not allow you to try to
< // change their mappings.
< if (arch_reg < numLogicalIntRegs) {
< DPRINTF(Rename, "Rename Map: Integer register %i being set to %i.\n",
< (int)arch_reg, renamed_reg);
---
> RegIndex rel_arch_reg;
236,239c151,153
< intRenameMap[arch_reg].physical_reg = renamed_reg;
< } else if (arch_reg < numLogicalIntRegs + numLogicalFloatRegs) {
< DPRINTF(Rename, "Rename Map: Float register %i being set to %i.\n",
< (int)arch_reg - numLogicalIntRegs, renamed_reg);
---
> switch (regIdxToClass(arch_reg, &rel_arch_reg)) {
> case IntRegClass:
> return setIntEntry(rel_arch_reg, phys_reg);
241,243c155,156
< floatRenameMap[arch_reg].physical_reg = renamed_reg;
< }
< }
---
> case FloatRegClass:
> return setFloatEntry(rel_arch_reg, phys_reg);
245,249c158,164
< int
< SimpleRenameMap::numFreeEntries()
< {
< int free_int_regs = freeList->numFreeIntRegs();
< int free_float_regs = freeList->numFreeFloatRegs();
---
> case MiscRegClass:
> // Misc registers do not actually rename, so don't change
> // their mappings. We end up here when a commit or squash
> // tries to update or undo a hardwired misc reg nmapping,
> // which should always be setting it to what it already is.
> assert(phys_reg == lookupMisc(rel_arch_reg));
> return;
251,254c166,168
< if (free_int_regs < free_float_regs) {
< return free_int_regs;
< } else {
< return free_float_regs;
---
> default:
> panic("rename setEntry(): unknown reg class %s\n",
> RegClassStrings[regIdxToClass(arch_reg)]);