35a36
> #include "cpu/reg_class_impl.hh"
43c44
< : freeList(NULL), zeroReg(0)
---
> : freeList(NULL), zeroReg(IntRegClass,0)
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< zeroReg = _zeroReg;
---
> zeroReg = RegId(IntRegClass, _zeroReg);
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< SimpleRenameMap::rename(RegIndex arch_reg)
---
> SimpleRenameMap::rename(const RegId& arch_reg)
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<
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< PhysRegIdPtr prev_reg = map[arch_reg];
---
> PhysRegIdPtr prev_reg = map[arch_reg.index()];
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< map[arch_reg] = renamed_reg;
---
> map[arch_reg.index()] = renamed_reg;
83,84c83,84
< arch_reg, renamed_reg->regIdx, renamed_reg->flatIdx,
< prev_reg->regIdx, prev_reg->flatIdx);
---
> arch_reg, renamed_reg->index(), renamed_reg->flatIndex(),
> prev_reg->index(), prev_reg->flatIndex());
108,179d107
<
< UnifiedRenameMap::RenameInfo
< UnifiedRenameMap::rename(RegId arch_reg)
< {
< switch (arch_reg.regClass) {
< case IntRegClass:
< return renameInt(arch_reg.regIdx);
<
< case FloatRegClass:
< return renameFloat(arch_reg.regIdx);
<
< case CCRegClass:
< return renameCC(arch_reg.regIdx);
<
< case MiscRegClass:
< return renameMisc(arch_reg.regIdx);
<
< default:
< panic("rename rename(): unknown reg class %s\n",
< RegClassStrings[arch_reg.regClass]);
< }
< }
<
<
< PhysRegIdPtr
< UnifiedRenameMap::lookup(RegId arch_reg) const
< {
< switch (arch_reg.regClass) {
< case IntRegClass:
< return lookupInt(arch_reg.regIdx);
<
< case FloatRegClass:
< return lookupFloat(arch_reg.regIdx);
<
< case CCRegClass:
< return lookupCC(arch_reg.regIdx);
<
< case MiscRegClass:
< return lookupMisc(arch_reg.regIdx);
<
< default:
< panic("rename lookup(): unknown reg class %s\n",
< RegClassStrings[arch_reg.regClass]);
< }
< }
<
< void
< UnifiedRenameMap::setEntry(RegId arch_reg, PhysRegIdPtr phys_reg)
< {
< switch (arch_reg.regClass) {
< case IntRegClass:
< return setIntEntry(arch_reg.regIdx, phys_reg);
<
< case FloatRegClass:
< return setFloatEntry(arch_reg.regIdx, phys_reg);
<
< case CCRegClass:
< return setCCEntry(arch_reg.regIdx, phys_reg);
<
< case MiscRegClass:
< // Misc registers do not actually rename, so don't change
< // their mappings. We end up here when a commit or squash
< // tries to update or undo a hardwired misc reg nmapping,
< // which should always be setting it to what it already is.
< assert(phys_reg == lookupMisc(arch_reg.regIdx));
< return;
<
< default:
< panic("rename setEntry(): unknown reg class %s\n",
< RegClassStrings[arch_reg.regClass]);
< }
< }