rename_map.cc (3867:807483cfab77) rename_map.cc (4030:4046b2213995)
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#include <vector>
32
33#include "cpu/o3/rename_map.hh"
34
35using namespace std;
36
37// @todo: Consider making inline bool functions that determine if the
38// register is a logical int, logical fp, physical int, physical fp,
39// etc.
40
41SimpleRenameMap::~SimpleRenameMap()
42{
43}
44
45void
46SimpleRenameMap::init(unsigned _numLogicalIntRegs,
47 unsigned _numPhysicalIntRegs,
48 PhysRegIndex &ireg_idx,
49
50 unsigned _numLogicalFloatRegs,
51 unsigned _numPhysicalFloatRegs,
52 PhysRegIndex &freg_idx,
53
54 unsigned _numMiscRegs,
55
56 RegIndex _intZeroReg,
57 RegIndex _floatZeroReg,
58
59 int map_id,
60 bool bindRegs)
61{
62 id = map_id;
63
64 numLogicalIntRegs = _numLogicalIntRegs;
65
66 numLogicalFloatRegs = _numLogicalFloatRegs;
67
68 numPhysicalIntRegs = _numPhysicalIntRegs;
69
70 numPhysicalFloatRegs = _numPhysicalFloatRegs;
71
72 numMiscRegs = _numMiscRegs;
73
74 intZeroReg = _intZeroReg;
75 floatZeroReg = _floatZeroReg;
76
77 DPRINTF(Rename, "Creating rename map %i. Phys: %i / %i, Float: "
78 "%i / %i.\n", id, numLogicalIntRegs, numPhysicalIntRegs,
79 numLogicalFloatRegs, numPhysicalFloatRegs);
80
81 numLogicalRegs = numLogicalIntRegs + numLogicalFloatRegs;
82
83 numPhysicalRegs = numPhysicalIntRegs + numPhysicalFloatRegs;
84
85 //Create the rename maps
86 intRenameMap.resize(numLogicalIntRegs);
87 floatRenameMap.resize(numLogicalRegs);
88
89 if (bindRegs) {
90 DPRINTF(Rename, "Binding registers into rename map %i",id);
91
92 // Initialize the entries in the integer rename map to point to the
93 // physical registers of the same index
94 for (RegIndex index = 0; index < numLogicalIntRegs; ++index)
95 {
96 intRenameMap[index].physical_reg = ireg_idx++;
97 }
98
99 // Initialize the entries in the floating point rename map to point to
100 // the physical registers of the same index
101 // Although the index refers purely to architected registers, because
102 // the floating reg indices come after the integer reg indices, they
103 // may exceed the size of a normal RegIndex (short).
104 for (PhysRegIndex index = numLogicalIntRegs;
105 index < numLogicalRegs; ++index)
106 {
107 floatRenameMap[index].physical_reg = freg_idx++;
108 }
109 } else {
110 DPRINTF(Rename, "Binding registers into rename map %i",id);
111
112 PhysRegIndex temp_ireg = ireg_idx;
113
114 for (RegIndex index = 0; index < numLogicalIntRegs; ++index)
115 {
116 intRenameMap[index].physical_reg = temp_ireg++;
117 }
118
119 PhysRegIndex temp_freg = freg_idx;
120
121 for (PhysRegIndex index = numLogicalIntRegs;
122 index < numLogicalRegs; ++index)
123 {
124 floatRenameMap[index].physical_reg = temp_freg++;
125 }
126 }
127}
128
129void
130SimpleRenameMap::setFreeList(SimpleFreeList *fl_ptr)
131{
132 freeList = fl_ptr;
133}
134
135
136SimpleRenameMap::RenameInfo
137SimpleRenameMap::rename(RegIndex arch_reg)
138{
139 PhysRegIndex renamed_reg;
140 PhysRegIndex prev_reg;
141
142 if (arch_reg < numLogicalIntRegs) {
143
144 // Record the current physical register that is renamed to the
145 // requested architected register.
146 prev_reg = intRenameMap[arch_reg].physical_reg;
147
148 // If it's not referencing the zero register, then rename the
149 // register.
150 if (arch_reg != intZeroReg) {
151 renamed_reg = freeList->getIntReg();
152
153 intRenameMap[arch_reg].physical_reg = renamed_reg;
154
155 assert(renamed_reg >= 0 && renamed_reg < numPhysicalIntRegs);
156
157 } else {
158 // Otherwise return the zero register so nothing bad happens.
159 renamed_reg = intZeroReg;
160 }
161 } else if (arch_reg < numLogicalRegs) {
162 // Record the current physical register that is renamed to the
163 // requested architected register.
164 prev_reg = floatRenameMap[arch_reg].physical_reg;
165
166 // If it's not referencing the zero register, then rename the
167 // register.
168 if (arch_reg != floatZeroReg) {
169 renamed_reg = freeList->getFloatReg();
170
171 floatRenameMap[arch_reg].physical_reg = renamed_reg;
172
173 assert(renamed_reg < numPhysicalRegs &&
174 renamed_reg >= numPhysicalIntRegs);
175 } else {
176 // Otherwise return the zero register so nothing bad happens.
177 renamed_reg = floatZeroReg;
178 }
179 } else {
180 // Subtract off the base offset for miscellaneous registers.
181 arch_reg = arch_reg - numLogicalRegs;
182
183 DPRINTF(Rename, "Renamed misc reg %d\n", arch_reg);
184
185 // No renaming happens to the misc. registers. They are
186 // simply the registers that come after all the physical
187 // registers; thus take the base architected register and add
188 // the physical registers to it.
189 renamed_reg = arch_reg + numPhysicalRegs;
190
191 // Set the previous register to the same register; mainly it must be
192 // known that the prev reg was outside the range of normal registers
193 // so the free list can avoid adding it.
194 prev_reg = renamed_reg;
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#include <vector>
32
33#include "cpu/o3/rename_map.hh"
34
35using namespace std;
36
37// @todo: Consider making inline bool functions that determine if the
38// register is a logical int, logical fp, physical int, physical fp,
39// etc.
40
41SimpleRenameMap::~SimpleRenameMap()
42{
43}
44
45void
46SimpleRenameMap::init(unsigned _numLogicalIntRegs,
47 unsigned _numPhysicalIntRegs,
48 PhysRegIndex &ireg_idx,
49
50 unsigned _numLogicalFloatRegs,
51 unsigned _numPhysicalFloatRegs,
52 PhysRegIndex &freg_idx,
53
54 unsigned _numMiscRegs,
55
56 RegIndex _intZeroReg,
57 RegIndex _floatZeroReg,
58
59 int map_id,
60 bool bindRegs)
61{
62 id = map_id;
63
64 numLogicalIntRegs = _numLogicalIntRegs;
65
66 numLogicalFloatRegs = _numLogicalFloatRegs;
67
68 numPhysicalIntRegs = _numPhysicalIntRegs;
69
70 numPhysicalFloatRegs = _numPhysicalFloatRegs;
71
72 numMiscRegs = _numMiscRegs;
73
74 intZeroReg = _intZeroReg;
75 floatZeroReg = _floatZeroReg;
76
77 DPRINTF(Rename, "Creating rename map %i. Phys: %i / %i, Float: "
78 "%i / %i.\n", id, numLogicalIntRegs, numPhysicalIntRegs,
79 numLogicalFloatRegs, numPhysicalFloatRegs);
80
81 numLogicalRegs = numLogicalIntRegs + numLogicalFloatRegs;
82
83 numPhysicalRegs = numPhysicalIntRegs + numPhysicalFloatRegs;
84
85 //Create the rename maps
86 intRenameMap.resize(numLogicalIntRegs);
87 floatRenameMap.resize(numLogicalRegs);
88
89 if (bindRegs) {
90 DPRINTF(Rename, "Binding registers into rename map %i",id);
91
92 // Initialize the entries in the integer rename map to point to the
93 // physical registers of the same index
94 for (RegIndex index = 0; index < numLogicalIntRegs; ++index)
95 {
96 intRenameMap[index].physical_reg = ireg_idx++;
97 }
98
99 // Initialize the entries in the floating point rename map to point to
100 // the physical registers of the same index
101 // Although the index refers purely to architected registers, because
102 // the floating reg indices come after the integer reg indices, they
103 // may exceed the size of a normal RegIndex (short).
104 for (PhysRegIndex index = numLogicalIntRegs;
105 index < numLogicalRegs; ++index)
106 {
107 floatRenameMap[index].physical_reg = freg_idx++;
108 }
109 } else {
110 DPRINTF(Rename, "Binding registers into rename map %i",id);
111
112 PhysRegIndex temp_ireg = ireg_idx;
113
114 for (RegIndex index = 0; index < numLogicalIntRegs; ++index)
115 {
116 intRenameMap[index].physical_reg = temp_ireg++;
117 }
118
119 PhysRegIndex temp_freg = freg_idx;
120
121 for (PhysRegIndex index = numLogicalIntRegs;
122 index < numLogicalRegs; ++index)
123 {
124 floatRenameMap[index].physical_reg = temp_freg++;
125 }
126 }
127}
128
129void
130SimpleRenameMap::setFreeList(SimpleFreeList *fl_ptr)
131{
132 freeList = fl_ptr;
133}
134
135
136SimpleRenameMap::RenameInfo
137SimpleRenameMap::rename(RegIndex arch_reg)
138{
139 PhysRegIndex renamed_reg;
140 PhysRegIndex prev_reg;
141
142 if (arch_reg < numLogicalIntRegs) {
143
144 // Record the current physical register that is renamed to the
145 // requested architected register.
146 prev_reg = intRenameMap[arch_reg].physical_reg;
147
148 // If it's not referencing the zero register, then rename the
149 // register.
150 if (arch_reg != intZeroReg) {
151 renamed_reg = freeList->getIntReg();
152
153 intRenameMap[arch_reg].physical_reg = renamed_reg;
154
155 assert(renamed_reg >= 0 && renamed_reg < numPhysicalIntRegs);
156
157 } else {
158 // Otherwise return the zero register so nothing bad happens.
159 renamed_reg = intZeroReg;
160 }
161 } else if (arch_reg < numLogicalRegs) {
162 // Record the current physical register that is renamed to the
163 // requested architected register.
164 prev_reg = floatRenameMap[arch_reg].physical_reg;
165
166 // If it's not referencing the zero register, then rename the
167 // register.
168 if (arch_reg != floatZeroReg) {
169 renamed_reg = freeList->getFloatReg();
170
171 floatRenameMap[arch_reg].physical_reg = renamed_reg;
172
173 assert(renamed_reg < numPhysicalRegs &&
174 renamed_reg >= numPhysicalIntRegs);
175 } else {
176 // Otherwise return the zero register so nothing bad happens.
177 renamed_reg = floatZeroReg;
178 }
179 } else {
180 // Subtract off the base offset for miscellaneous registers.
181 arch_reg = arch_reg - numLogicalRegs;
182
183 DPRINTF(Rename, "Renamed misc reg %d\n", arch_reg);
184
185 // No renaming happens to the misc. registers. They are
186 // simply the registers that come after all the physical
187 // registers; thus take the base architected register and add
188 // the physical registers to it.
189 renamed_reg = arch_reg + numPhysicalRegs;
190
191 // Set the previous register to the same register; mainly it must be
192 // known that the prev reg was outside the range of normal registers
193 // so the free list can avoid adding it.
194 prev_reg = renamed_reg;
195
196 assert(renamed_reg < numPhysicalRegs + numMiscRegs);
197 }
198
199 DPRINTF(Rename, "Renamed reg %d to physical reg %d old mapping was %d\n",
200 arch_reg, renamed_reg, prev_reg);
201
202 return RenameInfo(renamed_reg, prev_reg);
203}
204
205PhysRegIndex
206SimpleRenameMap::lookup(RegIndex arch_reg)
207{
208 if (arch_reg < numLogicalIntRegs) {
209 return intRenameMap[arch_reg].physical_reg;
210 } else if (arch_reg < numLogicalRegs) {
211 return floatRenameMap[arch_reg].physical_reg;
212 } else {
213 // Subtract off the misc registers offset.
214 arch_reg = arch_reg - numLogicalRegs;
215
216 // Misc. regs don't rename, so simply add the base arch reg to
217 // the number of physical registers.
218 return numPhysicalRegs + arch_reg;
219 }
220}
221
222void
223SimpleRenameMap::setEntry(RegIndex arch_reg, PhysRegIndex renamed_reg)
224{
225 // In this implementation the miscellaneous registers do not
226 // actually rename, so this function does not allow you to try to
227 // change their mappings.
228 if (arch_reg < numLogicalIntRegs) {
229 DPRINTF(Rename, "Rename Map: Integer register %i being set to %i.\n",
230 (int)arch_reg, renamed_reg);
231
232 intRenameMap[arch_reg].physical_reg = renamed_reg;
233 } else if (arch_reg < numLogicalIntRegs + numLogicalFloatRegs) {
234 DPRINTF(Rename, "Rename Map: Float register %i being set to %i.\n",
235 (int)arch_reg - numLogicalIntRegs, renamed_reg);
236
237 floatRenameMap[arch_reg].physical_reg = renamed_reg;
238 }
239}
240
241int
242SimpleRenameMap::numFreeEntries()
243{
244 int free_int_regs = freeList->numFreeIntRegs();
245 int free_float_regs = freeList->numFreeFloatRegs();
246
247 if (free_int_regs < free_float_regs) {
248 return free_int_regs;
249 } else {
250 return free_float_regs;
251 }
252}
195 }
196
197 DPRINTF(Rename, "Renamed reg %d to physical reg %d old mapping was %d\n",
198 arch_reg, renamed_reg, prev_reg);
199
200 return RenameInfo(renamed_reg, prev_reg);
201}
202
203PhysRegIndex
204SimpleRenameMap::lookup(RegIndex arch_reg)
205{
206 if (arch_reg < numLogicalIntRegs) {
207 return intRenameMap[arch_reg].physical_reg;
208 } else if (arch_reg < numLogicalRegs) {
209 return floatRenameMap[arch_reg].physical_reg;
210 } else {
211 // Subtract off the misc registers offset.
212 arch_reg = arch_reg - numLogicalRegs;
213
214 // Misc. regs don't rename, so simply add the base arch reg to
215 // the number of physical registers.
216 return numPhysicalRegs + arch_reg;
217 }
218}
219
220void
221SimpleRenameMap::setEntry(RegIndex arch_reg, PhysRegIndex renamed_reg)
222{
223 // In this implementation the miscellaneous registers do not
224 // actually rename, so this function does not allow you to try to
225 // change their mappings.
226 if (arch_reg < numLogicalIntRegs) {
227 DPRINTF(Rename, "Rename Map: Integer register %i being set to %i.\n",
228 (int)arch_reg, renamed_reg);
229
230 intRenameMap[arch_reg].physical_reg = renamed_reg;
231 } else if (arch_reg < numLogicalIntRegs + numLogicalFloatRegs) {
232 DPRINTF(Rename, "Rename Map: Float register %i being set to %i.\n",
233 (int)arch_reg - numLogicalIntRegs, renamed_reg);
234
235 floatRenameMap[arch_reg].physical_reg = renamed_reg;
236 }
237}
238
239int
240SimpleRenameMap::numFreeEntries()
241{
242 int free_int_regs = freeList->numFreeIntRegs();
243 int free_float_regs = freeList->numFreeFloatRegs();
244
245 if (free_int_regs < free_float_regs) {
246 return free_int_regs;
247 } else {
248 return free_float_regs;
249 }
250}