3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2005 The Regents of The University of Michigan
15 * Copyright (c) 2013 Advanced Micro Devices, Inc.
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 */
43
44#include "cpu/o3/rename_map.hh"
45
46#include <vector>
47
48#include "cpu/reg_class.hh"
49#include "debug/Rename.hh"
50
51using namespace std;
52
53/**** SimpleRenameMap methods ****/
54
55SimpleRenameMap::SimpleRenameMap()
56 : freeList(NULL), zeroReg(IntRegClass,0)
57{
58}
59
60
61void
62SimpleRenameMap::init(unsigned size, SimpleFreeList *_freeList,
63 RegIndex _zeroReg)
64{
65 assert(freeList == NULL);
66 assert(map.empty());
67
68 map.resize(size);
69 freeList = _freeList;
70 zeroReg = RegId(IntRegClass, _zeroReg);
71}
72
73SimpleRenameMap::RenameInfo
74SimpleRenameMap::rename(const RegId& arch_reg)
75{
76 PhysRegIdPtr renamed_reg;
77 // Record the current physical register that is renamed to the
78 // requested architected register.
79 PhysRegIdPtr prev_reg = map[arch_reg.flatIndex()];
80
81 // If it's not referencing the zero register, then rename the
82 // register.
83 if (arch_reg != zeroReg) {
84 renamed_reg = freeList->getReg();
85
86 map[arch_reg.flatIndex()] = renamed_reg;
87 } else {
88 // Otherwise return the zero register so nothing bad happens.
89 assert(prev_reg->isZeroReg());
90 renamed_reg = prev_reg;
91 }
92
93 DPRINTF(Rename, "Renamed reg %d to physical reg %d (%d) old mapping was"
94 " %d (%d)\n",
95 arch_reg, renamed_reg->flatIndex(), renamed_reg->flatIndex(),
96 prev_reg->flatIndex(), prev_reg->flatIndex());
97
98 return RenameInfo(renamed_reg, prev_reg);
99}
100
101
102/**** UnifiedRenameMap methods ****/
103
104void
105UnifiedRenameMap::init(PhysRegFile *_regFile,
106 RegIndex _intZeroReg,
107 RegIndex _floatZeroReg,
108 UnifiedFreeList *freeList,
109 VecMode _mode)
110{
111 regFile = _regFile;
112 vecMode = _mode;
113
114 intMap.init(TheISA::NumIntRegs, &(freeList->intList), _intZeroReg);
115
116 floatMap.init(TheISA::NumFloatRegs, &(freeList->floatList), _floatZeroReg);
117
118 vecMap.init(TheISA::NumVecRegs, &(freeList->vecList), (RegIndex)-1);
119
120 vecElemMap.init(TheISA::NumVecRegs * NVecElems,
121 &(freeList->vecElemList), (RegIndex)-1);
122
| 3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2005 The Regents of The University of Michigan
15 * Copyright (c) 2013 Advanced Micro Devices, Inc.
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 */
43
44#include "cpu/o3/rename_map.hh"
45
46#include <vector>
47
48#include "cpu/reg_class.hh"
49#include "debug/Rename.hh"
50
51using namespace std;
52
53/**** SimpleRenameMap methods ****/
54
55SimpleRenameMap::SimpleRenameMap()
56 : freeList(NULL), zeroReg(IntRegClass,0)
57{
58}
59
60
61void
62SimpleRenameMap::init(unsigned size, SimpleFreeList *_freeList,
63 RegIndex _zeroReg)
64{
65 assert(freeList == NULL);
66 assert(map.empty());
67
68 map.resize(size);
69 freeList = _freeList;
70 zeroReg = RegId(IntRegClass, _zeroReg);
71}
72
73SimpleRenameMap::RenameInfo
74SimpleRenameMap::rename(const RegId& arch_reg)
75{
76 PhysRegIdPtr renamed_reg;
77 // Record the current physical register that is renamed to the
78 // requested architected register.
79 PhysRegIdPtr prev_reg = map[arch_reg.flatIndex()];
80
81 // If it's not referencing the zero register, then rename the
82 // register.
83 if (arch_reg != zeroReg) {
84 renamed_reg = freeList->getReg();
85
86 map[arch_reg.flatIndex()] = renamed_reg;
87 } else {
88 // Otherwise return the zero register so nothing bad happens.
89 assert(prev_reg->isZeroReg());
90 renamed_reg = prev_reg;
91 }
92
93 DPRINTF(Rename, "Renamed reg %d to physical reg %d (%d) old mapping was"
94 " %d (%d)\n",
95 arch_reg, renamed_reg->flatIndex(), renamed_reg->flatIndex(),
96 prev_reg->flatIndex(), prev_reg->flatIndex());
97
98 return RenameInfo(renamed_reg, prev_reg);
99}
100
101
102/**** UnifiedRenameMap methods ****/
103
104void
105UnifiedRenameMap::init(PhysRegFile *_regFile,
106 RegIndex _intZeroReg,
107 RegIndex _floatZeroReg,
108 UnifiedFreeList *freeList,
109 VecMode _mode)
110{
111 regFile = _regFile;
112 vecMode = _mode;
113
114 intMap.init(TheISA::NumIntRegs, &(freeList->intList), _intZeroReg);
115
116 floatMap.init(TheISA::NumFloatRegs, &(freeList->floatList), _floatZeroReg);
117
118 vecMap.init(TheISA::NumVecRegs, &(freeList->vecList), (RegIndex)-1);
119
120 vecElemMap.init(TheISA::NumVecRegs * NVecElems,
121 &(freeList->vecElemList), (RegIndex)-1);
122
|
123 ccMap.init(TheISA::NumCCRegs, &(freeList->ccList), (RegIndex)-1);
124
125}
126
127void
128UnifiedRenameMap::switchFreeList(UnifiedFreeList* freeList)
129{
130 if (vecMode == Enums::Elem) {
131
132 /* The free list should currently be tracking full registers. */
133 panic_if(freeList->hasFreeVecElems(),
134 "The free list is already tracking Vec elems");
135 panic_if(freeList->numFreeVecRegs() !=
136 regFile->numVecPhysRegs() - TheISA::NumVecRegs,
137 "The free list has lost vector registers");
138
139 /* Split the free regs. */
140 while (freeList->hasFreeVecRegs()) {
141 auto vr = freeList->getVecReg();
142 auto range = this->regFile->getRegElemIds(vr);
143 freeList->addRegs(range.first, range.second);
144 }
145
146 } else if (vecMode == Enums::Full) {
147
148 /* The free list should currently be tracking register elems. */
149 panic_if(freeList->hasFreeVecRegs(),
150 "The free list is already tracking full Vec");
151 panic_if(freeList->numFreeVecElems() !=
152 regFile->numVecElemPhysRegs() - TheISA::NumFloatRegs,
153 "The free list has lost vector register elements");
154
155 auto range = regFile->getRegIds(VecRegClass);
156 freeList->addRegs(range.first + TheISA::NumVecRegs, range.second);
157
158 /* We remove the elems from the free list. */
159 while (freeList->hasFreeVecElems())
160 freeList->getVecElem();
161 }
162}
163
164void
165UnifiedRenameMap::switchMode(VecMode newVecMode)
166{
167 if (newVecMode == Enums::Elem && vecMode == Enums::Full) {
168
169 /* Switch to vector element rename mode. */
170 vecMode = Enums::Elem;
171
172 /* Split the mapping of each arch reg. */
173 int vec_idx = 0;
174 for (auto &vec: vecMap) {
175 PhysRegFile::IdRange range = this->regFile->getRegElemIds(vec);
176 auto idx = 0;
177 for (auto phys_elem = range.first;
178 phys_elem < range.second; idx++, phys_elem++) {
179
180 setEntry(RegId(VecElemClass, vec_idx, idx), &(*phys_elem));
181 }
182 vec_idx++;
183 }
184
185 } else if (newVecMode == Enums::Full && vecMode == Enums::Elem) {
186
187 /* Switch to full vector register rename mode. */
188 vecMode = Enums::Full;
189
190 /* To rebuild the arch regs we take the easy road:
191 * 1.- Stitch the elems together into vectors.
192 * 2.- Replace the contents of the register file with the vectors
193 * 3.- Set the remaining registers as free
194 */
195 TheISA::VecRegContainer new_RF[TheISA::NumVecRegs];
196 for (uint32_t i = 0; i < TheISA::NumVecRegs; i++) {
197 VecReg dst = new_RF[i].as<TheISA::VecElem>();
198 for (uint32_t l = 0; l < NVecElems; l++) {
199 RegId s_rid(VecElemClass, i, l);
200 PhysRegIdPtr s_prid = vecElemMap.lookup(s_rid);
201 dst[l] = regFile->readVecElem(s_prid);
202 }
203 }
204
205 for (uint32_t i = 0; i < TheISA::NumVecRegs; i++) {
206 PhysRegId pregId(VecRegClass, i, 0);
207 regFile->setVecReg(regFile->getTrueId(&pregId), new_RF[i]);
208 }
209
210 }
211}
| 125 ccMap.init(TheISA::NumCCRegs, &(freeList->ccList), (RegIndex)-1);
126
127}
128
129void
130UnifiedRenameMap::switchFreeList(UnifiedFreeList* freeList)
131{
132 if (vecMode == Enums::Elem) {
133
134 /* The free list should currently be tracking full registers. */
135 panic_if(freeList->hasFreeVecElems(),
136 "The free list is already tracking Vec elems");
137 panic_if(freeList->numFreeVecRegs() !=
138 regFile->numVecPhysRegs() - TheISA::NumVecRegs,
139 "The free list has lost vector registers");
140
141 /* Split the free regs. */
142 while (freeList->hasFreeVecRegs()) {
143 auto vr = freeList->getVecReg();
144 auto range = this->regFile->getRegElemIds(vr);
145 freeList->addRegs(range.first, range.second);
146 }
147
148 } else if (vecMode == Enums::Full) {
149
150 /* The free list should currently be tracking register elems. */
151 panic_if(freeList->hasFreeVecRegs(),
152 "The free list is already tracking full Vec");
153 panic_if(freeList->numFreeVecElems() !=
154 regFile->numVecElemPhysRegs() - TheISA::NumFloatRegs,
155 "The free list has lost vector register elements");
156
157 auto range = regFile->getRegIds(VecRegClass);
158 freeList->addRegs(range.first + TheISA::NumVecRegs, range.second);
159
160 /* We remove the elems from the free list. */
161 while (freeList->hasFreeVecElems())
162 freeList->getVecElem();
163 }
164}
165
166void
167UnifiedRenameMap::switchMode(VecMode newVecMode)
168{
169 if (newVecMode == Enums::Elem && vecMode == Enums::Full) {
170
171 /* Switch to vector element rename mode. */
172 vecMode = Enums::Elem;
173
174 /* Split the mapping of each arch reg. */
175 int vec_idx = 0;
176 for (auto &vec: vecMap) {
177 PhysRegFile::IdRange range = this->regFile->getRegElemIds(vec);
178 auto idx = 0;
179 for (auto phys_elem = range.first;
180 phys_elem < range.second; idx++, phys_elem++) {
181
182 setEntry(RegId(VecElemClass, vec_idx, idx), &(*phys_elem));
183 }
184 vec_idx++;
185 }
186
187 } else if (newVecMode == Enums::Full && vecMode == Enums::Elem) {
188
189 /* Switch to full vector register rename mode. */
190 vecMode = Enums::Full;
191
192 /* To rebuild the arch regs we take the easy road:
193 * 1.- Stitch the elems together into vectors.
194 * 2.- Replace the contents of the register file with the vectors
195 * 3.- Set the remaining registers as free
196 */
197 TheISA::VecRegContainer new_RF[TheISA::NumVecRegs];
198 for (uint32_t i = 0; i < TheISA::NumVecRegs; i++) {
199 VecReg dst = new_RF[i].as<TheISA::VecElem>();
200 for (uint32_t l = 0; l < NVecElems; l++) {
201 RegId s_rid(VecElemClass, i, l);
202 PhysRegIdPtr s_prid = vecElemMap.lookup(s_rid);
203 dst[l] = regFile->readVecElem(s_prid);
204 }
205 }
206
207 for (uint32_t i = 0; i < TheISA::NumVecRegs; i++) {
208 PhysRegId pregId(VecRegClass, i, 0);
209 regFile->setVecReg(regFile->getTrueId(&pregId), new_RF[i]);
210 }
211
212 }
213}
|