rename_map.cc (2670:9107b8bd08cd) | rename_map.cc (3867:807483cfab77) |
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1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 166 unchanged lines hidden (view full) --- 175 } else { 176 // Otherwise return the zero register so nothing bad happens. 177 renamed_reg = floatZeroReg; 178 } 179 } else { 180 // Subtract off the base offset for miscellaneous registers. 181 arch_reg = arch_reg - numLogicalRegs; 182 | 1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 166 unchanged lines hidden (view full) --- 175 } else { 176 // Otherwise return the zero register so nothing bad happens. 177 renamed_reg = floatZeroReg; 178 } 179 } else { 180 // Subtract off the base offset for miscellaneous registers. 181 arch_reg = arch_reg - numLogicalRegs; 182 |
183 DPRINTF(Rename, "Renamed misc reg %d\n", arch_reg); 184 |
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183 // No renaming happens to the misc. registers. They are 184 // simply the registers that come after all the physical 185 // registers; thus take the base architected register and add 186 // the physical registers to it. 187 renamed_reg = arch_reg + numPhysicalRegs; 188 189 // Set the previous register to the same register; mainly it must be 190 // known that the prev reg was outside the range of normal registers 191 // so the free list can avoid adding it. 192 prev_reg = renamed_reg; 193 194 assert(renamed_reg < numPhysicalRegs + numMiscRegs); 195 } 196 | 185 // No renaming happens to the misc. registers. They are 186 // simply the registers that come after all the physical 187 // registers; thus take the base architected register and add 188 // the physical registers to it. 189 renamed_reg = arch_reg + numPhysicalRegs; 190 191 // Set the previous register to the same register; mainly it must be 192 // known that the prev reg was outside the range of normal registers 193 // so the free list can avoid adding it. 194 prev_reg = renamed_reg; 195 196 assert(renamed_reg < numPhysicalRegs + numMiscRegs); 197 } 198 |
199 DPRINTF(Rename, "Renamed reg %d to physical reg %d old mapping was %d\n", 200 arch_reg, renamed_reg, prev_reg); 201 |
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197 return RenameInfo(renamed_reg, prev_reg); 198} 199 200PhysRegIndex 201SimpleRenameMap::lookup(RegIndex arch_reg) 202{ 203 if (arch_reg < numLogicalIntRegs) { 204 return intRenameMap[arch_reg].physical_reg; --- 43 unchanged lines hidden --- | 202 return RenameInfo(renamed_reg, prev_reg); 203} 204 205PhysRegIndex 206SimpleRenameMap::lookup(RegIndex arch_reg) 207{ 208 if (arch_reg < numLogicalIntRegs) { 209 return intRenameMap[arch_reg].physical_reg; --- 43 unchanged lines hidden --- |