1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Kevin Lim
30 */
31
32#include <vector>
33
34#include "cpu/o3/rename_map.hh"
35#include "debug/Rename.hh"
36
37using namespace std;
38
39/**** SimpleRenameMap methods ****/
40
41SimpleRenameMap::SimpleRenameMap()
42 : freeList(NULL)
43{
44}
45
46
47void
48SimpleRenameMap::init(unsigned size, SimpleFreeList *_freeList,
49 RegIndex _zeroReg)
50{
51 assert(freeList == NULL);
52 assert(map.empty());
53
54 map.resize(size);
55 freeList = _freeList;
56 zeroReg = _zeroReg;
57}
58
59SimpleRenameMap::RenameInfo
60SimpleRenameMap::rename(RegIndex arch_reg)
61{
62 PhysRegIndex renamed_reg;
63
64 // Record the current physical register that is renamed to the
65 // requested architected register.
66 PhysRegIndex prev_reg = map[arch_reg];
67
68 // If it's not referencing the zero register, then rename the
69 // register.
70 if (arch_reg != zeroReg) {
71 renamed_reg = freeList->getReg();
72
73 map[arch_reg] = renamed_reg;
74 } else {
75 // Otherwise return the zero register so nothing bad happens.
76 assert(prev_reg == zeroReg);
77 renamed_reg = zeroReg;
78 }
79
80 DPRINTF(Rename, "Renamed reg %d to physical reg %d old mapping was %d\n",
81 arch_reg, renamed_reg, prev_reg);
82
83 return RenameInfo(renamed_reg, prev_reg);
84}
85
86
87/**** UnifiedRenameMap methods ****/
88
89void
90UnifiedRenameMap::init(PhysRegFile *_regFile,
91 RegIndex _intZeroReg,
92 RegIndex _floatZeroReg,
93 UnifiedFreeList *freeList)
94{
95 regFile = _regFile;
96
97 intMap.init(TheISA::NumIntRegs, &(freeList->intList), _intZeroReg);
98
99 floatMap.init(TheISA::NumFloatRegs, &(freeList->floatList), _floatZeroReg);
100}
101
102
103UnifiedRenameMap::RenameInfo
104UnifiedRenameMap::rename(RegIndex arch_reg)
105{
106 RegIndex rel_arch_reg;
107
108 switch (regIdxToClass(arch_reg, &rel_arch_reg)) {
109 case IntRegClass:
110 return renameInt(rel_arch_reg);
111
112 case FloatRegClass:
113 return renameFloat(rel_arch_reg);
114
115 case MiscRegClass:
116 return renameMisc(rel_arch_reg);
117
118 default:
119 panic("rename rename(): unknown reg class %s\n",
120 RegClassStrings[regIdxToClass(arch_reg)]);
121 }
122}
123
124
125PhysRegIndex
126UnifiedRenameMap::lookup(RegIndex arch_reg) const
127{
128 RegIndex rel_arch_reg;
129
130 switch (regIdxToClass(arch_reg, &rel_arch_reg)) {
131 case IntRegClass:
132 return lookupInt(rel_arch_reg);
133
134 case FloatRegClass:
135 return lookupFloat(rel_arch_reg);
136
137 case MiscRegClass:
138 return lookupMisc(rel_arch_reg);
139
140 default:
141 panic("rename lookup(): unknown reg class %s\n",
142 RegClassStrings[regIdxToClass(arch_reg)]);
143 }
144}
145
146void
147UnifiedRenameMap::setEntry(RegIndex arch_reg, PhysRegIndex phys_reg)
148{
149 RegIndex rel_arch_reg;
150
151 switch (regIdxToClass(arch_reg, &rel_arch_reg)) {
152 case IntRegClass:
153 return setIntEntry(rel_arch_reg, phys_reg);
154
155 case FloatRegClass:
156 return setFloatEntry(rel_arch_reg, phys_reg);
157
158 case MiscRegClass:
159 // Misc registers do not actually rename, so don't change
160 // their mappings. We end up here when a commit or squash
161 // tries to update or undo a hardwired misc reg nmapping,
162 // which should always be setting it to what it already is.
163 assert(phys_reg == lookupMisc(rel_arch_reg));
164 return;
165
166 default:
167 panic("rename setEntry(): unknown reg class %s\n",
168 RegClassStrings[regIdxToClass(arch_reg)]);
169 }
170}