1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Kevin Lim
30 */
31
32#include "cpu/o3/rename_map.hh"
33
34#include <vector>
35
36#include "cpu/reg_class_impl.hh"
37#include "debug/Rename.hh"
38
39using namespace std;
40
41/**** SimpleRenameMap methods ****/
42
43SimpleRenameMap::SimpleRenameMap()
44 : freeList(NULL), zeroReg(IntRegClass,0)
45{
46}
47
48
49void
50SimpleRenameMap::init(unsigned size, SimpleFreeList *_freeList,
51 RegIndex _zeroReg)
52{
53 assert(freeList == NULL);
54 assert(map.empty());
55
56 map.resize(size);
57 freeList = _freeList;
58 zeroReg = RegId(IntRegClass, _zeroReg);
59}
60
61SimpleRenameMap::RenameInfo
62SimpleRenameMap::rename(const RegId& arch_reg)
63{
64 PhysRegIdPtr renamed_reg;
65 // Record the current physical register that is renamed to the
66 // requested architected register.
67 PhysRegIdPtr prev_reg = map[arch_reg.index()];
68
69 // If it's not referencing the zero register, then rename the
70 // register.
71 if (arch_reg != zeroReg) {
72 renamed_reg = freeList->getReg();
73
74 map[arch_reg.index()] = renamed_reg;
75 } else {
76 // Otherwise return the zero register so nothing bad happens.
77 assert(prev_reg->isZeroReg());
78 renamed_reg = prev_reg;
79 }
80
81 DPRINTF(Rename, "Renamed reg %d to physical reg %d (%d) old mapping was"
82 " %d (%d)\n",
83 arch_reg, renamed_reg->index(), renamed_reg->flatIndex(),
84 prev_reg->index(), prev_reg->flatIndex());
85
86 return RenameInfo(renamed_reg, prev_reg);
87}
88
89
90/**** UnifiedRenameMap methods ****/
91
92void
93UnifiedRenameMap::init(PhysRegFile *_regFile,
94 RegIndex _intZeroReg,
95 RegIndex _floatZeroReg,
96 UnifiedFreeList *freeList)
97{
98 regFile = _regFile;
99
100 intMap.init(TheISA::NumIntRegs, &(freeList->intList), _intZeroReg);
101
102 floatMap.init(TheISA::NumFloatRegs, &(freeList->floatList), _floatZeroReg);
103
104 ccMap.init(TheISA::NumCCRegs, &(freeList->ccList), (RegIndex)-1);
105
106}
107