rename_impl.hh (9919:803903a8dac1) | rename_impl.hh (9920:028e4da64b42) |
---|---|
1/* 2 * Copyright (c) 2010-2012 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved. 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 51 unchanged lines hidden (view full) --- 60DefaultRename<Impl>::DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params) 61 : cpu(_cpu), 62 iewToRenameDelay(params->iewToRenameDelay), 63 decodeToRenameDelay(params->decodeToRenameDelay), 64 commitToRenameDelay(params->commitToRenameDelay), 65 renameWidth(params->renameWidth), 66 commitWidth(params->commitWidth), 67 numThreads(params->numThreads), | 1/* 2 * Copyright (c) 2010-2012 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved. 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 51 unchanged lines hidden (view full) --- 60DefaultRename<Impl>::DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params) 61 : cpu(_cpu), 62 iewToRenameDelay(params->iewToRenameDelay), 63 decodeToRenameDelay(params->decodeToRenameDelay), 64 commitToRenameDelay(params->commitToRenameDelay), 65 renameWidth(params->renameWidth), 66 commitWidth(params->commitWidth), 67 numThreads(params->numThreads), |
68 maxPhysicalRegs(params->numPhysIntRegs + params->numPhysFloatRegs) | 68 maxPhysicalRegs(params->numPhysIntRegs + params->numPhysFloatRegs 69 + params->numPhysCCRegs) |
69{ 70 // @todo: Make into a parameter. 71 skidBufferMax = (2 * (decodeToRenameDelay * params->decodeWidth)) + renameWidth; 72} 73 74template <class Impl> 75std::string 76DefaultRename<Impl>::name() const --- 892 unchanged lines hidden (view full) --- 969 break; 970 971 case FloatRegClass: 972 flat_rel_src_reg = tc->flattenFloatIndex(rel_src_reg); 973 renamed_reg = map->lookupFloat(flat_rel_src_reg); 974 fpRenameLookups++; 975 break; 976 | 70{ 71 // @todo: Make into a parameter. 72 skidBufferMax = (2 * (decodeToRenameDelay * params->decodeWidth)) + renameWidth; 73} 74 75template <class Impl> 76std::string 77DefaultRename<Impl>::name() const --- 892 unchanged lines hidden (view full) --- 970 break; 971 972 case FloatRegClass: 973 flat_rel_src_reg = tc->flattenFloatIndex(rel_src_reg); 974 renamed_reg = map->lookupFloat(flat_rel_src_reg); 975 fpRenameLookups++; 976 break; 977 |
978 case CCRegClass: 979 flat_rel_src_reg = tc->flattenCCIndex(rel_src_reg); 980 renamed_reg = map->lookupCC(flat_rel_src_reg); 981 break; 982 |
|
977 case MiscRegClass: 978 // misc regs don't get flattened 979 flat_rel_src_reg = rel_src_reg; 980 renamed_reg = map->lookupMisc(flat_rel_src_reg); 981 break; 982 983 default: 984 panic("Reg index is out of bound: %d.", src_reg); --- 44 unchanged lines hidden (view full) --- 1029 break; 1030 1031 case FloatRegClass: 1032 flat_rel_dest_reg = tc->flattenFloatIndex(rel_dest_reg); 1033 rename_result = map->renameFloat(flat_rel_dest_reg); 1034 flat_uni_dest_reg = flat_rel_dest_reg + TheISA::FP_Reg_Base; 1035 break; 1036 | 983 case MiscRegClass: 984 // misc regs don't get flattened 985 flat_rel_src_reg = rel_src_reg; 986 renamed_reg = map->lookupMisc(flat_rel_src_reg); 987 break; 988 989 default: 990 panic("Reg index is out of bound: %d.", src_reg); --- 44 unchanged lines hidden (view full) --- 1035 break; 1036 1037 case FloatRegClass: 1038 flat_rel_dest_reg = tc->flattenFloatIndex(rel_dest_reg); 1039 rename_result = map->renameFloat(flat_rel_dest_reg); 1040 flat_uni_dest_reg = flat_rel_dest_reg + TheISA::FP_Reg_Base; 1041 break; 1042 |
1043 case CCRegClass: 1044 flat_rel_dest_reg = tc->flattenCCIndex(rel_dest_reg); 1045 rename_result = map->renameCC(flat_rel_dest_reg); 1046 flat_uni_dest_reg = flat_rel_dest_reg + TheISA::CC_Reg_Base; 1047 break; 1048 |
|
1037 case MiscRegClass: 1038 // misc regs don't get flattened 1039 flat_rel_dest_reg = rel_dest_reg; 1040 rename_result = map->renameMisc(flat_rel_dest_reg); 1041 flat_uni_dest_reg = flat_rel_dest_reg + TheISA::Misc_Reg_Base; 1042 break; 1043 1044 default: --- 332 unchanged lines hidden --- | 1049 case MiscRegClass: 1050 // misc regs don't get flattened 1051 flat_rel_dest_reg = rel_dest_reg; 1052 rename_result = map->renameMisc(flat_rel_dest_reg); 1053 flat_uni_dest_reg = flat_rel_dest_reg + TheISA::Misc_Reg_Base; 1054 break; 1055 1056 default: --- 332 unchanged lines hidden --- |