rename_impl.hh (9531:1114ead790eb) rename_impl.hh (9913:7f43babfde6a)
1/*
2 * Copyright (c) 2010-2012 ARM Limited
1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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42 */
43
44#include <list>
45
46#include "arch/isa_traits.hh"
47#include "arch/registers.hh"
48#include "config/the_isa.hh"
49#include "cpu/o3/rename.hh"
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated

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43 */
44
45#include <list>
46
47#include "arch/isa_traits.hh"
48#include "arch/registers.hh"
49#include "config/the_isa.hh"
50#include "cpu/o3/rename.hh"
51#include "cpu/reg_class.hh"
50#include "debug/Activity.hh"
51#include "debug/Rename.hh"
52#include "debug/O3PipeView.hh"
53#include "params/DerivO3CPU.hh"
54
55using namespace std;
56
57template <class Impl>

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943 unsigned num_src_regs = inst->numSrcRegs();
944
945 // Get the architectual register numbers from the source and
946 // destination operands, and redirect them to the right register.
947 // Will need to mark dependencies though.
948 for (int src_idx = 0; src_idx < num_src_regs; src_idx++) {
949 RegIndex src_reg = inst->srcRegIdx(src_idx);
950 RegIndex flat_src_reg = src_reg;
52#include "debug/Activity.hh"
53#include "debug/Rename.hh"
54#include "debug/O3PipeView.hh"
55#include "params/DerivO3CPU.hh"
56
57using namespace std;
58
59template <class Impl>

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945 unsigned num_src_regs = inst->numSrcRegs();
946
947 // Get the architectual register numbers from the source and
948 // destination operands, and redirect them to the right register.
949 // Will need to mark dependencies though.
950 for (int src_idx = 0; src_idx < num_src_regs; src_idx++) {
951 RegIndex src_reg = inst->srcRegIdx(src_idx);
952 RegIndex flat_src_reg = src_reg;
951 if (src_reg < TheISA::FP_Base_DepTag) {
953 switch (regIdxToClass(src_reg)) {
954 case IntRegClass:
952 flat_src_reg = inst->tcBase()->flattenIntIndex(src_reg);
953 DPRINTF(Rename, "Flattening index %d to %d.\n",
954 (int)src_reg, (int)flat_src_reg);
955 flat_src_reg = inst->tcBase()->flattenIntIndex(src_reg);
956 DPRINTF(Rename, "Flattening index %d to %d.\n",
957 (int)src_reg, (int)flat_src_reg);
955 } else if (src_reg < TheISA::Ctrl_Base_DepTag) {
958 break;
959
960 case FloatRegClass:
956 src_reg = src_reg - TheISA::FP_Base_DepTag;
957 flat_src_reg = inst->tcBase()->flattenFloatIndex(src_reg);
958 DPRINTF(Rename, "Flattening index %d to %d.\n",
959 (int)src_reg, (int)flat_src_reg);
960 flat_src_reg += TheISA::NumIntRegs;
961 src_reg = src_reg - TheISA::FP_Base_DepTag;
962 flat_src_reg = inst->tcBase()->flattenFloatIndex(src_reg);
963 DPRINTF(Rename, "Flattening index %d to %d.\n",
964 (int)src_reg, (int)flat_src_reg);
965 flat_src_reg += TheISA::NumIntRegs;
961 } else if (src_reg < TheISA::Max_DepTag) {
966 break;
967
968 case MiscRegClass:
962 flat_src_reg = src_reg - TheISA::Ctrl_Base_DepTag +
963 TheISA::NumFloatRegs + TheISA::NumIntRegs;
964 DPRINTF(Rename, "Adjusting reg index from %d to %d.\n",
965 src_reg, flat_src_reg);
969 flat_src_reg = src_reg - TheISA::Ctrl_Base_DepTag +
970 TheISA::NumFloatRegs + TheISA::NumIntRegs;
971 DPRINTF(Rename, "Adjusting reg index from %d to %d.\n",
972 src_reg, flat_src_reg);
966 } else {
973 break;
974
975 default:
967 panic("Reg index is out of bound: %d.", src_reg);
968 }
969
970 // Look up the source registers to get the phys. register they've
971 // been renamed to, and set the sources to those registers.
972 PhysRegIndex renamed_reg = renameMap[tid]->lookup(flat_src_reg);
973
974 DPRINTF(Rename, "[tid:%u]: Looking up arch reg %i, got "

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1000 typename RenameMap::RenameInfo rename_result;
1001
1002 unsigned num_dest_regs = inst->numDestRegs();
1003
1004 // Rename the destination registers.
1005 for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) {
1006 RegIndex dest_reg = inst->destRegIdx(dest_idx);
1007 RegIndex flat_dest_reg = dest_reg;
976 panic("Reg index is out of bound: %d.", src_reg);
977 }
978
979 // Look up the source registers to get the phys. register they've
980 // been renamed to, and set the sources to those registers.
981 PhysRegIndex renamed_reg = renameMap[tid]->lookup(flat_src_reg);
982
983 DPRINTF(Rename, "[tid:%u]: Looking up arch reg %i, got "

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1009 typename RenameMap::RenameInfo rename_result;
1010
1011 unsigned num_dest_regs = inst->numDestRegs();
1012
1013 // Rename the destination registers.
1014 for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) {
1015 RegIndex dest_reg = inst->destRegIdx(dest_idx);
1016 RegIndex flat_dest_reg = dest_reg;
1008 if (dest_reg < TheISA::FP_Base_DepTag) {
1017 switch (regIdxToClass(dest_reg)) {
1018 case IntRegClass:
1009 // Integer registers are flattened.
1010 flat_dest_reg = inst->tcBase()->flattenIntIndex(dest_reg);
1011 DPRINTF(Rename, "Flattening index %d to %d.\n",
1012 (int)dest_reg, (int)flat_dest_reg);
1019 // Integer registers are flattened.
1020 flat_dest_reg = inst->tcBase()->flattenIntIndex(dest_reg);
1021 DPRINTF(Rename, "Flattening index %d to %d.\n",
1022 (int)dest_reg, (int)flat_dest_reg);
1013 } else if (dest_reg < TheISA::Ctrl_Base_DepTag) {
1023 break;
1024
1025 case FloatRegClass:
1014 dest_reg = dest_reg - TheISA::FP_Base_DepTag;
1015 flat_dest_reg = inst->tcBase()->flattenFloatIndex(dest_reg);
1016 DPRINTF(Rename, "Flattening index %d to %d.\n",
1017 (int)dest_reg, (int)flat_dest_reg);
1018 flat_dest_reg += TheISA::NumIntRegs;
1026 dest_reg = dest_reg - TheISA::FP_Base_DepTag;
1027 flat_dest_reg = inst->tcBase()->flattenFloatIndex(dest_reg);
1028 DPRINTF(Rename, "Flattening index %d to %d.\n",
1029 (int)dest_reg, (int)flat_dest_reg);
1030 flat_dest_reg += TheISA::NumIntRegs;
1019 } else if (dest_reg < TheISA::Max_DepTag) {
1031 break;
1032
1033 case MiscRegClass:
1020 // Floating point and Miscellaneous registers need their indexes
1021 // adjusted to account for the expanded number of flattened int regs.
1022 flat_dest_reg = dest_reg - TheISA::Ctrl_Base_DepTag +
1023 TheISA::NumIntRegs + TheISA::NumFloatRegs;
1024 DPRINTF(Rename, "Adjusting reg index from %d to %d.\n",
1025 dest_reg, flat_dest_reg);
1034 // Floating point and Miscellaneous registers need their indexes
1035 // adjusted to account for the expanded number of flattened int regs.
1036 flat_dest_reg = dest_reg - TheISA::Ctrl_Base_DepTag +
1037 TheISA::NumIntRegs + TheISA::NumFloatRegs;
1038 DPRINTF(Rename, "Adjusting reg index from %d to %d.\n",
1039 dest_reg, flat_dest_reg);
1026 } else {
1040 break;
1041
1042 default:
1027 panic("Reg index is out of bound: %d.", dest_reg);
1028 }
1029
1030 inst->flattenDestReg(dest_idx, flat_dest_reg);
1031
1032 // Get the physical register that the destination will be
1033 // renamed to.
1034 rename_result = renameMap[tid]->rename(flat_dest_reg);
1035
1036 //Mark Scoreboard entry as not ready
1043 panic("Reg index is out of bound: %d.", dest_reg);
1044 }
1045
1046 inst->flattenDestReg(dest_idx, flat_dest_reg);
1047
1048 // Get the physical register that the destination will be
1049 // renamed to.
1050 rename_result = renameMap[tid]->rename(flat_dest_reg);
1051
1052 //Mark Scoreboard entry as not ready
1037 if (dest_reg < TheISA::Ctrl_Base_DepTag)
1053 if (regIdxToClass(dest_reg) != MiscRegClass)
1038 scoreboard->unsetReg(rename_result.first);
1039
1040 DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical "
1041 "reg %i.\n", tid, (int)flat_dest_reg,
1042 (int)rename_result.first);
1043
1044 // Record the rename information so that a history can be kept.
1045 RenameHistory hb_entry(inst->seqNum, flat_dest_reg,

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1055
1056 DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical "
1057 "reg %i.\n", tid, (int)flat_dest_reg,
1058 (int)rename_result.first);
1059
1060 // Record the rename information so that a history can be kept.
1061 RenameHistory hb_entry(inst->seqNum, flat_dest_reg,

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