rename_impl.hh (9527:68154bc0e0ea) rename_impl.hh (9531:1114ead790eb)
1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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595 --insts_available;
596
597 continue;
598 }
599
600 DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with "
601 "PC %s.\n", tid, inst->seqNum, inst->pcState());
602
1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 586 unchanged lines hidden (view full) ---

595 --insts_available;
596
597 continue;
598 }
599
600 DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with "
601 "PC %s.\n", tid, inst->seqNum, inst->pcState());
602
603 // Check here to make sure there are enough destination registers
604 // to rename to. Otherwise block.
605 if (renameMap[tid]->numFreeEntries() < inst->numDestRegs()) {
606 DPRINTF(Rename, "Blocking due to lack of free "
607 "physical registers to rename to.\n");
608 blockThisCycle = true;
609 insts_to_rename.push_front(inst);
610 ++renameFullRegistersEvents;
611
612 break;
613 }
614
603 // Handle serializeAfter/serializeBefore instructions.
604 // serializeAfter marks the next instruction as serializeBefore.
605 // serializeBefore makes the instruction wait in rename until the ROB
606 // is empty.
607
608 // In this model, IPR accesses are serialize before
609 // instructions, and store conditionals are serialize after
610 // instructions. This is mainly due to lack of support for

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636
637 renamedSerializing++;
638
639 inst->setSerializeHandled();
640
641 serializeAfter(insts_to_rename, tid);
642 }
643
615 // Handle serializeAfter/serializeBefore instructions.
616 // serializeAfter marks the next instruction as serializeBefore.
617 // serializeBefore makes the instruction wait in rename until the ROB
618 // is empty.
619
620 // In this model, IPR accesses are serialize before
621 // instructions, and store conditionals are serialize after
622 // instructions. This is mainly due to lack of support for

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648
649 renamedSerializing++;
650
651 inst->setSerializeHandled();
652
653 serializeAfter(insts_to_rename, tid);
654 }
655
644 // Check here to make sure there are enough destination registers
645 // to rename to. Otherwise block.
646 if (renameMap[tid]->numFreeEntries() < inst->numDestRegs()) {
647 DPRINTF(Rename, "Blocking due to lack of free "
648 "physical registers to rename to.\n");
649 blockThisCycle = true;
650 insts_to_rename.push_front(inst);
651 ++renameFullRegistersEvents;
652
653 break;
654 }
655
656 renameSrcRegs(inst, inst->threadNumber);
657
658 renameDestRegs(inst, inst->threadNumber);
659
660 ++renamed_insts;
661
662
663 // Put instruction in rename queue.

--- 700 unchanged lines hidden --- 		656 renameSrcRegs(inst, inst->threadNumber);
657
658 renameDestRegs(inst, inst->threadNumber);
659
660 ++renamed_insts;
661
662
663 // Put instruction in rename queue.

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