rename_impl.hh (9427:ddf45c1d54d4) rename_impl.hh (9444:ab47fe7f03f0)
1/*
1/*
2 * Copyright (c) 2010 ARM Limited
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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56template <class Impl>
57DefaultRename<Impl>::DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params)
58 : cpu(_cpu),
59 iewToRenameDelay(params->iewToRenameDelay),
60 decodeToRenameDelay(params->decodeToRenameDelay),
61 commitToRenameDelay(params->commitToRenameDelay),
62 renameWidth(params->renameWidth),
63 commitWidth(params->commitWidth),
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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56template <class Impl>
57DefaultRename<Impl>::DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params)
58 : cpu(_cpu),
59 iewToRenameDelay(params->iewToRenameDelay),
60 decodeToRenameDelay(params->decodeToRenameDelay),
61 commitToRenameDelay(params->commitToRenameDelay),
62 renameWidth(params->renameWidth),
63 commitWidth(params->commitWidth),
64 resumeSerialize(false),
65 resumeUnblocking(false),
66 numThreads(params->numThreads),
67 maxPhysicalRegs(params->numPhysIntRegs + params->numPhysFloatRegs)
68{
64 numThreads(params->numThreads),
65 maxPhysicalRegs(params->numPhysIntRegs + params->numPhysFloatRegs)
66{
69 _status = Inactive;
70
71 for (ThreadID tid = 0; tid < numThreads; tid++) {
72 renameStatus[tid] = Idle;
73
74 freeEntries[tid].iqEntries = 0;
75 freeEntries[tid].lsqEntries = 0;
76 freeEntries[tid].robEntries = 0;
77
78 stalls[tid].iew = false;
79 stalls[tid].commit = false;
80 serializeInst[tid] = NULL;
81
82 instsInProgress[tid] = 0;
83
84 emptyROB[tid] = true;
85
86 serializeOnNextInst[tid] = false;
87 }
88
89 // @todo: Make into a parameter.
90 skidBufferMax = (2 * (decodeToRenameDelay * params->decodeWidth)) + renameWidth;
91}
92
93template <class Impl>
94std::string
95DefaultRename<Impl>::name() const
96{

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225 // Setup wire to get information from decode.
226 fromDecode = decodeQueue->getWire(-decodeToRenameDelay);
227}
228
229template <class Impl>
230void
231DefaultRename<Impl>::startupStage()
232{
67 // @todo: Make into a parameter.
68 skidBufferMax = (2 * (decodeToRenameDelay * params->decodeWidth)) + renameWidth;
69}
70
71template <class Impl>
72std::string
73DefaultRename<Impl>::name() const
74{

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203 // Setup wire to get information from decode.
204 fromDecode = decodeQueue->getWire(-decodeToRenameDelay);
205}
206
207template <class Impl>
208void
209DefaultRename<Impl>::startupStage()
210{
211 resetStage();
212}
213
214template <class Impl>
215void
216DefaultRename<Impl>::resetStage()
217{
218 _status = Inactive;
219
220 resumeSerialize = false;
221 resumeUnblocking = false;
222
233 // Grab the number of free entries directly from the stages.
234 for (ThreadID tid = 0; tid < numThreads; tid++) {
223 // Grab the number of free entries directly from the stages.
224 for (ThreadID tid = 0; tid < numThreads; tid++) {
225 renameStatus[tid] = Idle;
226
235 freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid);
236 freeEntries[tid].lsqEntries = iew_ptr->ldstQueue.numFreeEntries(tid);
237 freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid);
238 emptyROB[tid] = true;
227 freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid);
228 freeEntries[tid].lsqEntries = iew_ptr->ldstQueue.numFreeEntries(tid);
229 freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid);
230 emptyROB[tid] = true;
231
232 stalls[tid].iew = false;
233 stalls[tid].commit = false;
234 serializeInst[tid] = NULL;
235
236 instsInProgress[tid] = 0;
237
238 serializeOnNextInst[tid] = false;
239 }
240}
241
242template<class Impl>
243void
244DefaultRename<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
245{
246 activeThreads = at_ptr;

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266void
267DefaultRename<Impl>::setScoreboard(Scoreboard *_scoreboard)
268{
269 scoreboard = _scoreboard;
270}
271
272template <class Impl>
273bool
239 }
240}
241
242template<class Impl>
243void
244DefaultRename<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
245{
246 activeThreads = at_ptr;

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266void
267DefaultRename<Impl>::setScoreboard(Scoreboard *_scoreboard)
268{
269 scoreboard = _scoreboard;
270}
271
272template <class Impl>
273bool
274DefaultRename<Impl>::drain()
274DefaultRename<Impl>::isDrained() const
275{
275{
276 // Rename is ready to switch out at any time.
277 cpu->signalDrained();
276 for (ThreadID tid = 0; tid < numThreads; tid++) {
277 if (instsInProgress[tid] != 0 ||
278 !historyBuffer[tid].empty() ||
279 !skidBuffer[tid].empty() ||
280 !insts[tid].empty())
281 return false;
282 }
278 return true;
279}
280
281template <class Impl>
282void
283 return true;
284}
285
286template <class Impl>
287void
283DefaultRename<Impl>::switchOut()
288DefaultRename<Impl>::takeOverFrom()
284{
289{
285 // Clear any state, fix up the rename map.
286 for (ThreadID tid = 0; tid < numThreads; tid++) {
287 typename std::list<RenameHistory>::iterator hb_it =
288 historyBuffer[tid].begin();
289
290 while (!historyBuffer[tid].empty()) {
291 assert(hb_it != historyBuffer[tid].end());
292
293 DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence "
294 "number %i.\n", tid, (*hb_it).instSeqNum);
295
296 // Tell the rename map to set the architected register to the
297 // previous physical register that it was renamed to.
298 renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg);
299
300 // Put the renamed physical register back on the free list.
301 freeList->addReg(hb_it->newPhysReg);
302
303 // Be sure to mark its register as ready if it's a misc register.
304 if (hb_it->newPhysReg >= maxPhysicalRegs) {
305 scoreboard->setReg(hb_it->newPhysReg);
306 }
307
308 historyBuffer[tid].erase(hb_it++);
309 }
310 insts[tid].clear();
311 skidBuffer[tid].clear();
312 }
290 resetStage();
313}
314
315template <class Impl>
316void
291}
292
293template <class Impl>
294void
317DefaultRename<Impl>::takeOverFrom()
295DefaultRename<Impl>::drainSanityCheck() const
318{
296{
319 _status = Inactive;
320 startupStage();
321
322 // Reset all state prior to taking over from the other CPU.
323 for (ThreadID tid = 0; tid < numThreads; tid++) {
297 for (ThreadID tid = 0; tid < numThreads; tid++) {
324 renameStatus[tid] = Idle;
325
326 stalls[tid].iew = false;
327 stalls[tid].commit = false;
328 serializeInst[tid] = NULL;
329
330 instsInProgress[tid] = 0;
331
332 emptyROB[tid] = true;
333
334 serializeOnNextInst[tid] = false;
298 assert(historyBuffer[tid].empty());
299 assert(insts[tid].empty());
300 assert(skidBuffer[tid].empty());
301 assert(instsInProgress[tid] == 0);
335 }
336}
337
338template <class Impl>
339void
340DefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, ThreadID tid)
341{
342 DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid);

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303}
304
305template <class Impl>
306void
307DefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, ThreadID tid)
308{
309 DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid);

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