rename_impl.hh (7720:65d338a8dba4) rename_impl.hh (7767:bf5377d8f5c1)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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954 // Get the architectual register numbers from the source and
955 // destination operands, and redirect them to the right register.
956 // Will need to mark dependencies though.
957 for (int src_idx = 0; src_idx < num_src_regs; src_idx++) {
958 RegIndex src_reg = inst->srcRegIdx(src_idx);
959 RegIndex flat_src_reg = src_reg;
960 if (src_reg < TheISA::FP_Base_DepTag) {
961 flat_src_reg = inst->tcBase()->flattenIntIndex(src_reg);
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 945 unchanged lines hidden (view full) ---

954 // Get the architectual register numbers from the source and
955 // destination operands, and redirect them to the right register.
956 // Will need to mark dependencies though.
957 for (int src_idx = 0; src_idx < num_src_regs; src_idx++) {
958 RegIndex src_reg = inst->srcRegIdx(src_idx);
959 RegIndex flat_src_reg = src_reg;
960 if (src_reg < TheISA::FP_Base_DepTag) {
961 flat_src_reg = inst->tcBase()->flattenIntIndex(src_reg);
962 DPRINTF(Rename, "Flattening index %d to %d.\n", (int)src_reg, (int)flat_src_reg);
962 DPRINTF(Rename, "Flattening index %d to %d.\n",
963 (int)src_reg, (int)flat_src_reg);
963 } else if (src_reg < TheISA::Ctrl_Base_DepTag) {
964 src_reg = src_reg - TheISA::FP_Base_DepTag;
965 flat_src_reg = inst->tcBase()->flattenFloatIndex(src_reg);
964 } else if (src_reg < TheISA::Ctrl_Base_DepTag) {
965 src_reg = src_reg - TheISA::FP_Base_DepTag;
966 flat_src_reg = inst->tcBase()->flattenFloatIndex(src_reg);
967 DPRINTF(Rename, "Flattening index %d to %d.\n",
968 (int)src_reg, (int)flat_src_reg);
966 flat_src_reg += TheISA::NumIntRegs;
967 } else if (src_reg < TheISA::Max_DepTag) {
969 flat_src_reg += TheISA::NumIntRegs;
970 } else if (src_reg < TheISA::Max_DepTag) {
968 flat_src_reg = src_reg - TheISA::FP_Base_DepTag + TheISA::NumIntRegs;
969 DPRINTF(Rename, "Adjusting reg index from %d to %d.\n", src_reg, flat_src_reg);
971 flat_src_reg = src_reg - TheISA::Ctrl_Base_DepTag +
972 TheISA::NumFloatRegs + TheISA::NumIntRegs;
973 DPRINTF(Rename, "Adjusting reg index from %d to %d.\n",
974 src_reg, flat_src_reg);
970 } else {
971 panic("Reg index is out of bound: %d.", src_reg);
972 }
973
974 inst->flattenSrcReg(src_idx, flat_src_reg);
975
976 // Look up the source registers to get the phys. register they've
977 // been renamed to, and set the sources to those registers.
978 PhysRegIndex renamed_reg = renameMap[tid]->lookup(flat_src_reg);
979
980 DPRINTF(Rename, "[tid:%u]: Looking up arch reg %i, got "
981 "physical reg %i.\n", tid, (int)flat_src_reg,
982 (int)renamed_reg);
983
984 inst->renameSrcReg(src_idx, renamed_reg);
985
986 // See if the register is ready or not.
987 if (scoreboard->getReg(renamed_reg) == true) {
975 } else {
976 panic("Reg index is out of bound: %d.", src_reg);
977 }
978
979 inst->flattenSrcReg(src_idx, flat_src_reg);
980
981 // Look up the source registers to get the phys. register they've
982 // been renamed to, and set the sources to those registers.
983 PhysRegIndex renamed_reg = renameMap[tid]->lookup(flat_src_reg);
984
985 DPRINTF(Rename, "[tid:%u]: Looking up arch reg %i, got "
986 "physical reg %i.\n", tid, (int)flat_src_reg,
987 (int)renamed_reg);
988
989 inst->renameSrcReg(src_idx, renamed_reg);
990
991 // See if the register is ready or not.
992 if (scoreboard->getReg(renamed_reg) == true) {
988 DPRINTF(Rename, "[tid:%u]: Register %d is ready.\n", tid, renamed_reg);
993 DPRINTF(Rename, "[tid:%u]: Register %d is ready.\n",
994 tid, renamed_reg);
989
990 inst->markSrcRegReady(src_idx);
991 } else {
995
996 inst->markSrcRegReady(src_idx);
997 } else {
992 DPRINTF(Rename, "[tid:%u]: Register %d is not ready.\n", tid, renamed_reg);
998 DPRINTF(Rename, "[tid:%u]: Register %d is not ready.\n",
999 tid, renamed_reg);
993 }
994
995 ++renameRenameLookups;
996 }
997}
998
999template <class Impl>
1000inline void

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1006
1007 // Rename the destination registers.
1008 for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) {
1009 RegIndex dest_reg = inst->destRegIdx(dest_idx);
1010 RegIndex flat_dest_reg = dest_reg;
1011 if (dest_reg < TheISA::FP_Base_DepTag) {
1012 // Integer registers are flattened.
1013 flat_dest_reg = inst->tcBase()->flattenIntIndex(dest_reg);
1000 }
1001
1002 ++renameRenameLookups;
1003 }
1004}
1005
1006template <class Impl>
1007inline void

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1013
1014 // Rename the destination registers.
1015 for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) {
1016 RegIndex dest_reg = inst->destRegIdx(dest_idx);
1017 RegIndex flat_dest_reg = dest_reg;
1018 if (dest_reg < TheISA::FP_Base_DepTag) {
1019 // Integer registers are flattened.
1020 flat_dest_reg = inst->tcBase()->flattenIntIndex(dest_reg);
1014 DPRINTF(Rename, "Flattening index %d to %d.\n", (int)dest_reg, (int)flat_dest_reg);
1021 DPRINTF(Rename, "Flattening index %d to %d.\n",
1022 (int)dest_reg, (int)flat_dest_reg);
1023 } else if (dest_reg < TheISA::Ctrl_Base_DepTag) {
1024 dest_reg = dest_reg - TheISA::FP_Base_DepTag;
1025 flat_dest_reg = inst->tcBase()->flattenFloatIndex(dest_reg);
1026 DPRINTF(Rename, "Flattening index %d to %d.\n",
1027 (int)dest_reg, (int)flat_dest_reg);
1028 flat_dest_reg += TheISA::NumIntRegs;
1015 } else if (dest_reg < TheISA::Max_DepTag) {
1016 // Floating point and Miscellaneous registers need their indexes
1017 // adjusted to account for the expanded number of flattened int regs.
1029 } else if (dest_reg < TheISA::Max_DepTag) {
1030 // Floating point and Miscellaneous registers need their indexes
1031 // adjusted to account for the expanded number of flattened int regs.
1018 flat_dest_reg = dest_reg - TheISA::FP_Base_DepTag + TheISA::NumIntRegs;
1019 DPRINTF(Rename, "Adjusting reg index from %d to %d.\n", dest_reg, flat_dest_reg);
1032 flat_dest_reg = dest_reg - TheISA::Ctrl_Base_DepTag +
1033 TheISA::NumIntRegs + TheISA::NumFloatRegs;
1034 DPRINTF(Rename, "Adjusting reg index from %d to %d.\n",
1035 dest_reg, flat_dest_reg);
1020 } else {
1021 panic("Reg index is out of bound: %d.", dest_reg);
1022 }
1023
1024 inst->flattenDestReg(dest_idx, flat_dest_reg);
1025
1026 // Get the physical register that the destination will be
1027 // renamed to.

--- 337 unchanged lines hidden --- 		1036 } else {
1037 panic("Reg index is out of bound: %d.", dest_reg);
1038 }
1039
1040 inst->flattenDestReg(dest_idx, flat_dest_reg);
1041
1042 // Get the physical register that the destination will be
1043 // renamed to.

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