rename_impl.hh (6658:f4de76601762) rename_impl.hh (7649:a6a6177a5ffa)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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961 RegIndex flat_src_reg = src_reg;
962 if (src_reg < TheISA::FP_Base_DepTag) {
963 flat_src_reg = inst->tcBase()->flattenIntIndex(src_reg);
964 DPRINTF(Rename, "Flattening index %d to %d.\n", (int)src_reg, (int)flat_src_reg);
965 } else if (src_reg < TheISA::Ctrl_Base_DepTag) {
966 src_reg = src_reg - TheISA::FP_Base_DepTag;
967 flat_src_reg = inst->tcBase()->flattenFloatIndex(src_reg);
968 flat_src_reg += TheISA::NumIntRegs;
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 952 unchanged lines hidden (view full) ---

961 RegIndex flat_src_reg = src_reg;
962 if (src_reg < TheISA::FP_Base_DepTag) {
963 flat_src_reg = inst->tcBase()->flattenIntIndex(src_reg);
964 DPRINTF(Rename, "Flattening index %d to %d.\n", (int)src_reg, (int)flat_src_reg);
965 } else if (src_reg < TheISA::Ctrl_Base_DepTag) {
966 src_reg = src_reg - TheISA::FP_Base_DepTag;
967 flat_src_reg = inst->tcBase()->flattenFloatIndex(src_reg);
968 flat_src_reg += TheISA::NumIntRegs;
969 } else {
969 } else if (src_reg < TheISA::Max_DepTag) {
970 flat_src_reg = src_reg - TheISA::FP_Base_DepTag + TheISA::NumIntRegs;
971 DPRINTF(Rename, "Adjusting reg index from %d to %d.\n", src_reg, flat_src_reg);
970 flat_src_reg = src_reg - TheISA::FP_Base_DepTag + TheISA::NumIntRegs;
971 DPRINTF(Rename, "Adjusting reg index from %d to %d.\n", src_reg, flat_src_reg);
972 } else {
973 panic("Reg index is out of bound: %d.", src_reg);
972 }
973
974 inst->flattenSrcReg(src_idx, flat_src_reg);
975
976 // Look up the source registers to get the phys. register they've
977 // been renamed to, and set the sources to those registers.
978 PhysRegIndex renamed_reg = renameMap[tid]->lookup(flat_src_reg);
979

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1007 // Rename the destination registers.
1008 for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) {
1009 RegIndex dest_reg = inst->destRegIdx(dest_idx);
1010 RegIndex flat_dest_reg = dest_reg;
1011 if (dest_reg < TheISA::FP_Base_DepTag) {
1012 // Integer registers are flattened.
1013 flat_dest_reg = inst->tcBase()->flattenIntIndex(dest_reg);
1014 DPRINTF(Rename, "Flattening index %d to %d.\n", (int)dest_reg, (int)flat_dest_reg);
974 }
975
976 inst->flattenSrcReg(src_idx, flat_src_reg);
977
978 // Look up the source registers to get the phys. register they've
979 // been renamed to, and set the sources to those registers.
980 PhysRegIndex renamed_reg = renameMap[tid]->lookup(flat_src_reg);
981

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1009 // Rename the destination registers.
1010 for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) {
1011 RegIndex dest_reg = inst->destRegIdx(dest_idx);
1012 RegIndex flat_dest_reg = dest_reg;
1013 if (dest_reg < TheISA::FP_Base_DepTag) {
1014 // Integer registers are flattened.
1015 flat_dest_reg = inst->tcBase()->flattenIntIndex(dest_reg);
1016 DPRINTF(Rename, "Flattening index %d to %d.\n", (int)dest_reg, (int)flat_dest_reg);
1015 } else {
1017 } else if (dest_reg < TheISA::Max_DepTag) {
1016 // Floating point and Miscellaneous registers need their indexes
1017 // adjusted to account for the expanded number of flattened int regs.
1018 flat_dest_reg = dest_reg - TheISA::FP_Base_DepTag + TheISA::NumIntRegs;
1019 DPRINTF(Rename, "Adjusting reg index from %d to %d.\n", dest_reg, flat_dest_reg);
1018 // Floating point and Miscellaneous registers need their indexes
1019 // adjusted to account for the expanded number of flattened int regs.
1020 flat_dest_reg = dest_reg - TheISA::FP_Base_DepTag + TheISA::NumIntRegs;
1021 DPRINTF(Rename, "Adjusting reg index from %d to %d.\n", dest_reg, flat_dest_reg);
1022 } else {
1023 panic("Reg index is out of bound: %d.", dest_reg);
1020 }
1021
1022 inst->flattenDestReg(dest_idx, flat_dest_reg);
1023
1024 // Get the physical register that the destination will be
1025 // renamed to.
1026 rename_result = renameMap[tid]->rename(flat_dest_reg);
1027

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1025
1026 inst->flattenDestReg(dest_idx, flat_dest_reg);
1027
1028 // Get the physical register that the destination will be
1029 // renamed to.
1030 rename_result = renameMap[tid]->rename(flat_dest_reg);
1031

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