rename_impl.hh (4357:f8b2da607906) rename_impl.hh (4632:be5b8f67b8fb)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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351 fromDecode->insts[i]->setSquashed();
352 wroteToTimeBuffer = true;
353 squashCount++;
354 }
355
356 }
357
358 // Clear the instruction list and skid buffer in case they have any
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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351 fromDecode->insts[i]->setSquashed();
352 wroteToTimeBuffer = true;
353 squashCount++;
354 }
355
356 }
357
358 // Clear the instruction list and skid buffer in case they have any
359 // insts in them. Since we support multiple ISAs, we cant just:
360 // "insts[tid].clear();" or "skidBuffer[tid].clear()" since there is
361 // a possible delay slot inst for different architectures
362 // insts[tid].clear();
363#if ISA_HAS_DELAY_SLOT
364 DPRINTF(Rename, "[tid:%i] Squashing incoming decode instructions until "
365 "[sn:%i].\n",tid, squash_seq_num);
366 ListIt ilist_it = insts[tid].begin();
367 while (ilist_it != insts[tid].end()) {
368 if ((*ilist_it)->seqNum > squash_seq_num) {
369 (*ilist_it)->setSquashed();
370 DPRINTF(Rename, "Squashing incoming decode instruction, "
371 "[tid:%i] [sn:%i] PC %08p.\n", tid, (*ilist_it)->seqNum, (*ilist_it)->PC);
372 }
373 ilist_it++;
374 }
375#else
359 // insts in them.
376 insts[tid].clear();
360 insts[tid].clear();
377#endif
378
379 // Clear the skid buffer in case it has any data in it.
361
362 // Clear the skid buffer in case it has any data in it.
380 // See comments above.
381 // skidBuffer[tid].clear();
382#if ISA_HAS_DELAY_SLOT
383 DPRINTF(Rename, "[tid:%i] Squashing incoming skidbuffer instructions "
384 "until [sn:%i].\n", tid, squash_seq_num);
385 ListIt slist_it = skidBuffer[tid].begin();
386 while (slist_it != skidBuffer[tid].end()) {
387 if ((*slist_it)->seqNum > squash_seq_num) {
388 (*slist_it)->setSquashed();
389 DPRINTF(Rename, "Squashing skidbuffer instruction, [tid:%i] [sn:%i]"
390 "PC %08p.\n", tid, (*slist_it)->seqNum, (*slist_it)->PC);
391 }
392 slist_it++;
393 }
394 resumeUnblocking = (skidBuffer[tid].size() != 0);
395 DPRINTF(Rename, "Resume unblocking set to %s\n",
396 resumeUnblocking ? "true" : "false");
397#else
398 skidBuffer[tid].clear();
363 skidBuffer[tid].clear();
399#endif
364
400 doSquash(squash_seq_num, tid);
401}
402
403template <class Impl>
404void
405DefaultRename<Impl>::tick()
406{
407 wroteToTimeBuffer = false;

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771}
772
773template <class Impl>
774void
775DefaultRename<Impl>::sortInsts()
776{
777 int insts_from_decode = fromDecode->size;
778#ifdef DEBUG
365 doSquash(squash_seq_num, tid);
366}
367
368template <class Impl>
369void
370DefaultRename<Impl>::tick()
371{
372 wroteToTimeBuffer = false;

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736}
737
738template <class Impl>
739void
740DefaultRename<Impl>::sortInsts()
741{
742 int insts_from_decode = fromDecode->size;
743#ifdef DEBUG
779#if !ISA_HAS_DELAY_SLOT
780 for (int i=0; i < numThreads; i++)
781 assert(insts[i].empty());
782#endif
744 for (int i=0; i < numThreads; i++)
745 assert(insts[i].empty());
746#endif
783#endif
784 for (int i = 0; i < insts_from_decode; ++i) {
785 DynInstPtr inst = fromDecode->insts[i];
786 insts[inst->threadNumber].push_back(inst);
787 }
788}
789
790template<class Impl>
791bool

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1243
1244 readFreeEntries(tid);
1245 readStallSignals(tid);
1246
1247 if (fromCommit->commitInfo[tid].squash) {
1248 DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from "
1249 "commit.\n", tid);
1250
747 for (int i = 0; i < insts_from_decode; ++i) {
748 DynInstPtr inst = fromDecode->insts[i];
749 insts[inst->threadNumber].push_back(inst);
750 }
751}
752
753template<class Impl>
754bool

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1206
1207 readFreeEntries(tid);
1208 readStallSignals(tid);
1209
1210 if (fromCommit->commitInfo[tid].squash) {
1211 DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from "
1212 "commit.\n", tid);
1213
1251#if ISA_HAS_DELAY_SLOT
1252 InstSeqNum squashed_seq_num = fromCommit->commitInfo[tid].bdelayDoneSeqNum;
1253#else
1254 InstSeqNum squashed_seq_num = fromCommit->commitInfo[tid].doneSeqNum;
1255#endif
1214 squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
1256
1215
1257 squash(squashed_seq_num, tid);
1258
1259 return true;
1260 }
1261
1262 if (fromCommit->commitInfo[tid].robSquashing) {
1263 DPRINTF(Rename, "[tid:%u]: ROB is still squashing.\n", tid);
1264
1265 renameStatus[tid] = Squashing;
1266

--- 132 unchanged lines hidden --- 		1216 return true;
1217 }
1218
1219 if (fromCommit->commitInfo[tid].robSquashing) {
1220 DPRINTF(Rename, "[tid:%u]: ROB is still squashing.\n", tid);
1221
1222 renameStatus[tid] = Squashing;
1223

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