rename_impl.hh (4345:a95454b0e835) rename_impl.hh (4352:52f11aaf7d19)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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687 }
688
689 // Check here to make sure there are enough destination registers
690 // to rename to. Otherwise block.
691 if (renameMap[tid]->numFreeEntries() < inst->numDestRegs()) {
692 DPRINTF(Rename, "Blocking due to lack of free "
693 "physical registers to rename to.\n");
694 blockThisCycle = true;
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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687 }
688
689 // Check here to make sure there are enough destination registers
690 // to rename to. Otherwise block.
691 if (renameMap[tid]->numFreeEntries() < inst->numDestRegs()) {
692 DPRINTF(Rename, "Blocking due to lack of free "
693 "physical registers to rename to.\n");
694 blockThisCycle = true;
695 insts_to_rename.push_front(inst);
695
696 ++renameFullRegistersEvents;
697
698 break;
699 }
700
701 renameSrcRegs(inst, inst->threadNumber);
702
703 renameDestRegs(inst, inst->threadNumber);

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991 // destination operands, and redirect them to the right register.
992 // Will need to mark dependencies though.
993 for (int src_idx = 0; src_idx < num_src_regs; src_idx++) {
994 RegIndex src_reg = inst->srcRegIdx(src_idx);
995 RegIndex flat_src_reg = src_reg;
996 if (src_reg < TheISA::FP_Base_DepTag) {
997 flat_src_reg = TheISA::flattenIntIndex(inst->tcBase(), src_reg);
998 DPRINTF(Rename, "Flattening index %d to %d.\n", (int)src_reg, (int)flat_src_reg);
696 ++renameFullRegistersEvents;
697
698 break;
699 }
700
701 renameSrcRegs(inst, inst->threadNumber);
702
703 renameDestRegs(inst, inst->threadNumber);

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991 // destination operands, and redirect them to the right register.
992 // Will need to mark dependencies though.
993 for (int src_idx = 0; src_idx < num_src_regs; src_idx++) {
994 RegIndex src_reg = inst->srcRegIdx(src_idx);
995 RegIndex flat_src_reg = src_reg;
996 if (src_reg < TheISA::FP_Base_DepTag) {
997 flat_src_reg = TheISA::flattenIntIndex(inst->tcBase(), src_reg);
998 DPRINTF(Rename, "Flattening index %d to %d.\n", (int)src_reg, (int)flat_src_reg);
999 } else {
1000 // Floating point and Miscellaneous registers need their indexes
1001 // adjusted to account for the expanded number of flattened int regs.
1002 flat_src_reg = src_reg - TheISA::FP_Base_DepTag + TheISA::NumIntRegs;
999 }
1003 }
1004
1000 inst->flattenSrcReg(src_idx, flat_src_reg);
1001
1002 // Look up the source registers to get the phys. register they've
1003 // been renamed to, and set the sources to those registers.
1004 PhysRegIndex renamed_reg = renameMap[tid]->lookup(flat_src_reg);
1005
1006 DPRINTF(Rename, "[tid:%u]: Looking up arch reg %i, got "
1007 "physical reg %i.\n", tid, (int)flat_src_reg,

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1028
1029 unsigned num_dest_regs = inst->numDestRegs();
1030
1031 // Rename the destination registers.
1032 for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) {
1033 RegIndex dest_reg = inst->destRegIdx(dest_idx);
1034 RegIndex flat_dest_reg = dest_reg;
1035 if (dest_reg < TheISA::FP_Base_DepTag) {
1005 inst->flattenSrcReg(src_idx, flat_src_reg);
1006
1007 // Look up the source registers to get the phys. register they've
1008 // been renamed to, and set the sources to those registers.
1009 PhysRegIndex renamed_reg = renameMap[tid]->lookup(flat_src_reg);
1010
1011 DPRINTF(Rename, "[tid:%u]: Looking up arch reg %i, got "
1012 "physical reg %i.\n", tid, (int)flat_src_reg,

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1033
1034 unsigned num_dest_regs = inst->numDestRegs();
1035
1036 // Rename the destination registers.
1037 for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) {
1038 RegIndex dest_reg = inst->destRegIdx(dest_idx);
1039 RegIndex flat_dest_reg = dest_reg;
1040 if (dest_reg < TheISA::FP_Base_DepTag) {
1041 // Integer registers are flattened.
1036 flat_dest_reg = TheISA::flattenIntIndex(inst->tcBase(), dest_reg);
1037 DPRINTF(Rename, "Flattening index %d to %d.\n", (int)dest_reg, (int)flat_dest_reg);
1042 flat_dest_reg = TheISA::flattenIntIndex(inst->tcBase(), dest_reg);
1043 DPRINTF(Rename, "Flattening index %d to %d.\n", (int)dest_reg, (int)flat_dest_reg);
1044 } else {
1045 // Floating point and Miscellaneous registers need their indexes
1046 // adjusted to account for the expanded number of flattened int regs.
1047 flat_dest_reg = dest_reg - TheISA::FP_Base_DepTag + TheISA::NumIntRegs;
1038 }
1039
1040 inst->flattenDestReg(dest_idx, flat_dest_reg);
1041
1042 // Get the physical register that the destination will be
1043 // renamed to.
1044 rename_result = renameMap[tid]->rename(flat_dest_reg);
1045

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1049
1050 inst->flattenDestReg(dest_idx, flat_dest_reg);
1051
1052 // Get the physical register that the destination will be
1053 // renamed to.
1054 rename_result = renameMap[tid]->rename(flat_dest_reg);
1055

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