rename_impl.hh (3867:807483cfab77) rename_impl.hh (3970:d54945bab95d)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 * Korey Sewell
30 */
31
32#include <list>
33
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 17 unchanged lines hidden (view full) ---

26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 * Korey Sewell
30 */
31
32#include <list>
33
34#include "arch/isa_traits.hh"
35#include "arch/regfile.hh"
34#include "config/full_system.hh"
35#include "cpu/o3/rename.hh"
36
37template <class Impl>
38DefaultRename<Impl>::DefaultRename(Params *params)
39 : iewToRenameDelay(params->iewToRenameDelay),
40 decodeToRenameDelay(params->decodeToRenameDelay),
41 commitToRenameDelay(params->commitToRenameDelay),
42 renameWidth(params->renameWidth),
43 commitWidth(params->commitWidth),
36#include "config/full_system.hh"
37#include "cpu/o3/rename.hh"
38
39template <class Impl>
40DefaultRename<Impl>::DefaultRename(Params *params)
41 : iewToRenameDelay(params->iewToRenameDelay),
42 decodeToRenameDelay(params->decodeToRenameDelay),
43 commitToRenameDelay(params->commitToRenameDelay),
44 renameWidth(params->renameWidth),
45 commitWidth(params->commitWidth),
46 resumeSerialize(false),
47 resumeUnblocking(false),
44 numThreads(params->numberOfThreads),
45 maxPhysicalRegs(params->numPhysIntRegs + params->numPhysFloatRegs)
46{
47 _status = Inactive;
48
49 for (int i=0; i< numThreads; i++) {
50 renameStatus[i] = Idle;
51

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327DefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, unsigned tid)
328{
329 DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid);
330
331 // Clear the stall signal if rename was blocked or unblocking before.
332 // If it still needs to block, the blocking should happen the next
333 // cycle and there should be space to hold everything due to the squash.
334 if (renameStatus[tid] == Blocked ||
48 numThreads(params->numberOfThreads),
49 maxPhysicalRegs(params->numPhysIntRegs + params->numPhysFloatRegs)
50{
51 _status = Inactive;
52
53 for (int i=0; i< numThreads; i++) {
54 renameStatus[i] = Idle;
55

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331DefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, unsigned tid)
332{
333 DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid);
334
335 // Clear the stall signal if rename was blocked or unblocking before.
336 // If it still needs to block, the blocking should happen the next
337 // cycle and there should be space to hold everything due to the squash.
338 if (renameStatus[tid] == Blocked ||
335 renameStatus[tid] == Unblocking ||
336 renameStatus[tid] == SerializeStall) {
337
339 renameStatus[tid] == Unblocking) {
338 toDecode->renameUnblock[tid] = 1;
339
340 toDecode->renameUnblock[tid] = 1;
341
342 resumeSerialize = false;
340 serializeInst[tid] = NULL;
343 serializeInst[tid] = NULL;
344 } else if (renameStatus[tid] == SerializeStall) {
345 if (serializeInst[tid]->seqNum <= squash_seq_num) {
346 DPRINTF(Rename, "Rename will resume serializing after squash\n");
347 resumeSerialize = true;
348 assert(serializeInst[tid]);
349 } else {
350 resumeSerialize = false;
351 toDecode->renameUnblock[tid] = 1;
352
353 serializeInst[tid] = NULL;
354 }
341 }
342
343 // Set the status to Squashing.
344 renameStatus[tid] = Squashing;
345
346 // Squash any instructions from decode.
347 unsigned squashCount = 0;
348

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387 while (slist_it != skidBuffer[tid].end()) {
388 if ((*slist_it)->seqNum > squash_seq_num) {
389 (*slist_it)->setSquashed();
390 DPRINTF(Rename, "Squashing skidbuffer instruction, [tid:%i] [sn:%i]"
391 "PC %08p.\n", tid, (*slist_it)->seqNum, (*slist_it)->PC);
392 }
393 slist_it++;
394 }
355 }
356
357 // Set the status to Squashing.
358 renameStatus[tid] = Squashing;
359
360 // Squash any instructions from decode.
361 unsigned squashCount = 0;
362

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401 while (slist_it != skidBuffer[tid].end()) {
402 if ((*slist_it)->seqNum > squash_seq_num) {
403 (*slist_it)->setSquashed();
404 DPRINTF(Rename, "Squashing skidbuffer instruction, [tid:%i] [sn:%i]"
405 "PC %08p.\n", tid, (*slist_it)->seqNum, (*slist_it)->PC);
406 }
407 slist_it++;
408 }
409 resumeUnblocking = (skidBuffer[tid].size() != 0);
410 DPRINTF(Rename, "Resume unblocking set to %s\n",
411 resumeUnblocking ? "true" : "false");
395#else
396 skidBuffer[tid].clear();
397#endif
398 doSquash(squash_seq_num, tid);
399}
400
401template <class Impl>
402void

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471 // check if stall conditions have passed
472
473 if (renameStatus[tid] == Blocked) {
474 ++renameBlockCycles;
475 } else if (renameStatus[tid] == Squashing) {
476 ++renameSquashCycles;
477 } else if (renameStatus[tid] == SerializeStall) {
478 ++renameSerializeStallCycles;
412#else
413 skidBuffer[tid].clear();
414#endif
415 doSquash(squash_seq_num, tid);
416}
417
418template <class Impl>
419void

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488 // check if stall conditions have passed
489
490 if (renameStatus[tid] == Blocked) {
491 ++renameBlockCycles;
492 } else if (renameStatus[tid] == Squashing) {
493 ++renameSquashCycles;
494 } else if (renameStatus[tid] == SerializeStall) {
495 ++renameSerializeStallCycles;
496 // If we are currently in SerializeStall and resumeSerialize
497 // was set, then that means that we are resuming serializing
498 // this cycle. Tell the previous stages to block.
499 if (resumeSerialize) {
500 resumeSerialize = false;
501 block(tid);
502 toDecode->renameUnblock[tid] = false;
503 }
504 } else if (renameStatus[tid] == Unblocking) {
505 if (resumeUnblocking) {
506 block(tid);
507 resumeUnblocking = false;
508 toDecode->renameUnblock[tid] = false;
509 }
479 }
480
481 if (renameStatus[tid] == Running ||
482 renameStatus[tid] == Idle) {
483 DPRINTF(Rename, "[tid:%u]: Not blocked, so attempting to run "
484 "stage.\n", tid);
485
486 renameInsts(tid);

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736 "skidBuffer\n", tid, inst->seqNum, inst->readPC());
737
738 ++renameSkidInsts;
739
740 skidBuffer[tid].push_back(inst);
741 }
742
743 if (skidBuffer[tid].size() > skidBufferMax)
510 }
511
512 if (renameStatus[tid] == Running ||
513 renameStatus[tid] == Idle) {
514 DPRINTF(Rename, "[tid:%u]: Not blocked, so attempting to run "
515 "stage.\n", tid);
516
517 renameInsts(tid);

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767 "skidBuffer\n", tid, inst->seqNum, inst->readPC());
768
769 ++renameSkidInsts;
770
771 skidBuffer[tid].push_back(inst);
772 }
773
774 if (skidBuffer[tid].size() > skidBufferMax)
775 {
776 typename InstQueue::iterator it;
777 warn("Skidbuffer contents:\n");
778 for(it = skidBuffer[tid].begin(); it != skidBuffer[tid].end(); it++)
779 {
780 warn("[tid:%u]: %s [sn:%i].\n", tid,
781 (*it)->staticInst->disassemble(inst->readPC()),
782 (*it)->seqNum);
783 }
744 panic("Skidbuffer Exceeded Max Size");
784 panic("Skidbuffer Exceeded Max Size");
785 }
745}
746
747template <class Impl>
748void
749DefaultRename<Impl>::sortInsts()
750{
751 int insts_from_decode = fromDecode->size;
752#ifdef DEBUG

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825
826 // Add the current inputs onto the skid buffer, so they can be
827 // reprocessed when this stage unblocks.
828 skidInsert(tid);
829
830 // Only signal backwards to block if the previous stages do not think
831 // rename is already blocked.
832 if (renameStatus[tid] != Blocked) {
786}
787
788template <class Impl>
789void
790DefaultRename<Impl>::sortInsts()
791{
792 int insts_from_decode = fromDecode->size;
793#ifdef DEBUG

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866
867 // Add the current inputs onto the skid buffer, so they can be
868 // reprocessed when this stage unblocks.
869 skidInsert(tid);
870
871 // Only signal backwards to block if the previous stages do not think
872 // rename is already blocked.
873 if (renameStatus[tid] != Blocked) {
833 if (renameStatus[tid] != Unblocking) {
874 // If resumeUnblocking is set, we unblocked during the squash,
875 // but now we're have unblocking status. We need to tell earlier
876 // stages to block.
877 if (resumeUnblocking || renameStatus[tid] != Unblocking) {
834 toDecode->renameBlock[tid] = true;
835 toDecode->renameUnblock[tid] = false;
836 wroteToTimeBuffer = true;
837 }
838
839 // Rename can not go from SerializeStall to Blocked, otherwise
840 // it would not know to complete the serialize stall.
841 if (renameStatus[tid] != SerializeStall) {

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958
959 unsigned num_src_regs = inst->numSrcRegs();
960
961 // Get the architectual register numbers from the source and
962 // destination operands, and redirect them to the right register.
963 // Will need to mark dependencies though.
964 for (int src_idx = 0; src_idx < num_src_regs; src_idx++) {
965 RegIndex src_reg = inst->srcRegIdx(src_idx);
878 toDecode->renameBlock[tid] = true;
879 toDecode->renameUnblock[tid] = false;
880 wroteToTimeBuffer = true;
881 }
882
883 // Rename can not go from SerializeStall to Blocked, otherwise
884 // it would not know to complete the serialize stall.
885 if (renameStatus[tid] != SerializeStall) {

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1002
1003 unsigned num_src_regs = inst->numSrcRegs();
1004
1005 // Get the architectual register numbers from the source and
1006 // destination operands, and redirect them to the right register.
1007 // Will need to mark dependencies though.
1008 for (int src_idx = 0; src_idx < num_src_regs; src_idx++) {
1009 RegIndex src_reg = inst->srcRegIdx(src_idx);
1010 RegIndex flat_src_reg = src_reg;
1011 if (src_reg < TheISA::FP_Base_DepTag) {
1012 flat_src_reg = TheISA::flattenIntIndex(inst->tcBase(), src_reg);
1013 DPRINTF(Rename, "Flattening index %d to %d.\n", (int)src_reg, (int)flat_src_reg);
1014 }
1015 inst->flattenSrcReg(src_idx, flat_src_reg);
966
967 // Look up the source registers to get the phys. register they've
968 // been renamed to, and set the sources to those registers.
1016
1017 // Look up the source registers to get the phys. register they've
1018 // been renamed to, and set the sources to those registers.
969 PhysRegIndex renamed_reg = renameMap[tid]->lookup(src_reg);
1019 PhysRegIndex renamed_reg = renameMap[tid]->lookup(flat_src_reg);
970
971 DPRINTF(Rename, "[tid:%u]: Looking up arch reg %i, got "
1020
1021 DPRINTF(Rename, "[tid:%u]: Looking up arch reg %i, got "
972 "physical reg %i.\n", tid, (int)src_reg,
1022 "physical reg %i.\n", tid, (int)flat_src_reg,
973 (int)renamed_reg);
974
975 inst->renameSrcReg(src_idx, renamed_reg);
976
977 // See if the register is ready or not.
978 if (scoreboard->getReg(renamed_reg) == true) {
979 DPRINTF(Rename, "[tid:%u]: Register is ready.\n", tid);
980

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991{
992 typename RenameMap::RenameInfo rename_result;
993
994 unsigned num_dest_regs = inst->numDestRegs();
995
996 // Rename the destination registers.
997 for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) {
998 RegIndex dest_reg = inst->destRegIdx(dest_idx);
1023 (int)renamed_reg);
1024
1025 inst->renameSrcReg(src_idx, renamed_reg);
1026
1027 // See if the register is ready or not.
1028 if (scoreboard->getReg(renamed_reg) == true) {
1029 DPRINTF(Rename, "[tid:%u]: Register is ready.\n", tid);
1030

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1041{
1042 typename RenameMap::RenameInfo rename_result;
1043
1044 unsigned num_dest_regs = inst->numDestRegs();
1045
1046 // Rename the destination registers.
1047 for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) {
1048 RegIndex dest_reg = inst->destRegIdx(dest_idx);
1049 RegIndex flat_dest_reg = dest_reg;
1050 if (dest_reg < TheISA::FP_Base_DepTag) {
1051 flat_dest_reg = TheISA::flattenIntIndex(inst->tcBase(), dest_reg);
1052 DPRINTF(Rename, "Flattening index %d to %d.\n", (int)dest_reg, (int)flat_dest_reg);
1053 }
999
1054
1055 inst->flattenDestReg(dest_idx, flat_dest_reg);
1056
1000 // Get the physical register that the destination will be
1001 // renamed to.
1057 // Get the physical register that the destination will be
1058 // renamed to.
1002 rename_result = renameMap[tid]->rename(dest_reg);
1059 rename_result = renameMap[tid]->rename(flat_dest_reg);
1003
1004 //Mark Scoreboard entry as not ready
1005 scoreboard->unsetReg(rename_result.first);
1006
1007 DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical "
1060
1061 //Mark Scoreboard entry as not ready
1062 scoreboard->unsetReg(rename_result.first);
1063
1064 DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical "
1008 "reg %i.\n", tid, (int)dest_reg,
1065 "reg %i.\n", tid, (int)flat_dest_reg,
1009 (int)rename_result.first);
1010
1011 // Record the rename information so that a history can be kept.
1066 (int)rename_result.first);
1067
1068 // Record the rename information so that a history can be kept.
1012 RenameHistory hb_entry(inst->seqNum, dest_reg,
1069 RenameHistory hb_entry(inst->seqNum, flat_dest_reg,
1013 rename_result.first,
1014 rename_result.second);
1015
1016 historyBuffer[tid].push_front(hb_entry);
1017
1018 DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer "
1019 "(size=%i), [sn:%lli].\n",tid,
1020 historyBuffer[tid].size(),

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1228 unblock(tid);
1229
1230 return true;
1231 }
1232
1233 if (renameStatus[tid] == Squashing) {
1234 // Switch status to running if rename isn't being told to block or
1235 // squash this cycle.
1070 rename_result.first,
1071 rename_result.second);
1072
1073 historyBuffer[tid].push_front(hb_entry);
1074
1075 DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer "
1076 "(size=%i), [sn:%lli].\n",tid,
1077 historyBuffer[tid].size(),

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1285 unblock(tid);
1286
1287 return true;
1288 }
1289
1290 if (renameStatus[tid] == Squashing) {
1291 // Switch status to running if rename isn't being told to block or
1292 // squash this cycle.
1236 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n",
1237 tid);
1293 if (resumeSerialize) {
1294 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to serialize.\n",
1295 tid);
1238
1296
1239 renameStatus[tid] = Running;
1297 renameStatus[tid] = SerializeStall;
1298 return true;
1299 } else if (resumeUnblocking) {
1300 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to unblocking.\n",
1301 tid);
1302 renameStatus[tid] = Unblocking;
1303 return true;
1304 } else {
1305 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n",
1306 tid);
1240
1307
1241 return false;
1308 renameStatus[tid] = Running;
1309 return false;
1310 }
1242 }
1243
1244 if (renameStatus[tid] == SerializeStall) {
1245 // Stall ends once the ROB is free.
1246 DPRINTF(Rename, "[tid:%u]: Done with serialize stall, switching to "
1247 "unblocking.\n", tid);
1248
1249 DynInstPtr serial_inst = serializeInst[tid];

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1312
1313 if (renameStatus[tid] == SerializeStall) {
1314 // Stall ends once the ROB is free.
1315 DPRINTF(Rename, "[tid:%u]: Done with serialize stall, switching to "
1316 "unblocking.\n", tid);
1317
1318 DynInstPtr serial_inst = serializeInst[tid];

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