rename_impl.hh (2980:eab855f06b79) rename_impl.hh (3093:b09c33e66bce)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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350
351 }
352
353 // Clear the instruction list and skid buffer in case they have any
354 // insts in them. Since we support multiple ISAs, we cant just:
355 // "insts[tid].clear();" or "skidBuffer[tid].clear()" since there is
356 // a possible delay slot inst for different architectures
357 // insts[tid].clear();
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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350
351 }
352
353 // Clear the instruction list and skid buffer in case they have any
354 // insts in them. Since we support multiple ISAs, we cant just:
355 // "insts[tid].clear();" or "skidBuffer[tid].clear()" since there is
356 // a possible delay slot inst for different architectures
357 // insts[tid].clear();
358#if THE_ISA == ALPHA_ISA
359 insts[tid].clear();
360#else
358#if ISA_HAS_DELAY_SLOT
361 DPRINTF(Rename, "[tid:%i] Squashing incoming decode instructions until "
362 "[sn:%i].\n",tid, squash_seq_num);
363 ListIt ilist_it = insts[tid].begin();
364 while (ilist_it != insts[tid].end()) {
365 if ((*ilist_it)->seqNum > squash_seq_num) {
366 (*ilist_it)->setSquashed();
367 DPRINTF(Rename, "Squashing incoming decode instruction, "
368 "[tid:%i] [sn:%i] PC %08p.\n", tid, (*ilist_it)->seqNum, (*ilist_it)->PC);
369 }
370 ilist_it++;
371 }
359 DPRINTF(Rename, "[tid:%i] Squashing incoming decode instructions until "
360 "[sn:%i].\n",tid, squash_seq_num);
361 ListIt ilist_it = insts[tid].begin();
362 while (ilist_it != insts[tid].end()) {
363 if ((*ilist_it)->seqNum > squash_seq_num) {
364 (*ilist_it)->setSquashed();
365 DPRINTF(Rename, "Squashing incoming decode instruction, "
366 "[tid:%i] [sn:%i] PC %08p.\n", tid, (*ilist_it)->seqNum, (*ilist_it)->PC);
367 }
368 ilist_it++;
369 }
370#else
371 insts[tid].clear();
372#endif
373
374 // Clear the skid buffer in case it has any data in it.
375 // See comments above.
376 // skidBuffer[tid].clear();
372#endif
373
374 // Clear the skid buffer in case it has any data in it.
375 // See comments above.
376 // skidBuffer[tid].clear();
377#if THE_ISA == ALPHA_ISA
378 skidBuffer[tid].clear();
379#else
377#if ISA_HAS_DELAY_SLOT
380 DPRINTF(Rename, "[tid:%i] Squashing incoming skidbuffer instructions "
381 "until [sn:%i].\n", tid, squash_seq_num);
382 ListIt slist_it = skidBuffer[tid].begin();
383 while (slist_it != skidBuffer[tid].end()) {
384 if ((*slist_it)->seqNum > squash_seq_num) {
385 (*slist_it)->setSquashed();
386 DPRINTF(Rename, "Squashing skidbuffer instruction, [tid:%i] [sn:%i]"
387 "PC %08p.\n", tid, (*slist_it)->seqNum, (*slist_it)->PC);
388 }
389 slist_it++;
390 }
378 DPRINTF(Rename, "[tid:%i] Squashing incoming skidbuffer instructions "
379 "until [sn:%i].\n", tid, squash_seq_num);
380 ListIt slist_it = skidBuffer[tid].begin();
381 while (slist_it != skidBuffer[tid].end()) {
382 if ((*slist_it)->seqNum > squash_seq_num) {
383 (*slist_it)->setSquashed();
384 DPRINTF(Rename, "Squashing skidbuffer instruction, [tid:%i] [sn:%i]"
385 "PC %08p.\n", tid, (*slist_it)->seqNum, (*slist_it)->PC);
386 }
387 slist_it++;
388 }
389#else
390 skidBuffer[tid].clear();
391#endif
392 doSquash(squash_seq_num, tid);
393}
394
395template <class Impl>
396void
397DefaultRename<Impl>::tick()
398{

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738}
739
740template <class Impl>
741void
742DefaultRename<Impl>::sortInsts()
743{
744 int insts_from_decode = fromDecode->size;
745#ifdef DEBUG
391#endif
392 doSquash(squash_seq_num, tid);
393}
394
395template <class Impl>
396void
397DefaultRename<Impl>::tick()
398{

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738}
739
740template <class Impl>
741void
742DefaultRename<Impl>::sortInsts()
743{
744 int insts_from_decode = fromDecode->size;
745#ifdef DEBUG
746#if THE_ISA == ALPHA_ISA
746#if !ISA_HAS_DELAY_SLOT
747 for (int i=0; i < numThreads; i++)
748 assert(insts[i].empty());
749#endif
750#endif
751 for (int i = 0; i < insts_from_decode; ++i) {
752 DynInstPtr inst = fromDecode->insts[i];
753 insts[inst->threadNumber].push_back(inst);
754 }

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1177
1178 readFreeEntries(tid);
1179 readStallSignals(tid);
1180
1181 if (fromCommit->commitInfo[tid].squash) {
1182 DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from "
1183 "commit.\n", tid);
1184
747 for (int i=0; i < numThreads; i++)
748 assert(insts[i].empty());
749#endif
750#endif
751 for (int i = 0; i < insts_from_decode; ++i) {
752 DynInstPtr inst = fromDecode->insts[i];
753 insts[inst->threadNumber].push_back(inst);
754 }

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1177
1178 readFreeEntries(tid);
1179 readStallSignals(tid);
1180
1181 if (fromCommit->commitInfo[tid].squash) {
1182 DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from "
1183 "commit.\n", tid);
1184
1185#if THE_ISA == ALPHA_ISA
1186 InstSeqNum squashed_seq_num = fromCommit->commitInfo[tid].doneSeqNum;
1187#else
1185#if ISA_HAS_DELAY_SLOT
1188 InstSeqNum squashed_seq_num = fromCommit->commitInfo[tid].bdelayDoneSeqNum;
1186 InstSeqNum squashed_seq_num = fromCommit->commitInfo[tid].bdelayDoneSeqNum;
1187#else
1188 InstSeqNum squashed_seq_num = fromCommit->commitInfo[tid].doneSeqNum;
1189#endif
1190
1191 squash(squashed_seq_num, tid);
1192
1193 return true;
1194 }
1195
1196 if (fromCommit->commitInfo[tid].robSquashing) {

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1190
1191 squash(squashed_seq_num, tid);
1192
1193 return true;
1194 }
1195
1196 if (fromCommit->commitInfo[tid].robSquashing) {

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