rename_impl.hh (2654:9559cfa91b9d) rename_impl.hh (2665:a124942bacb8)
1/*
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the

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19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the

--- 8 unchanged lines hidden (view full) ---

19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
27 */
28
29#include <list>
30
31#include "config/full_system.hh"
32#include "cpu/o3/rename.hh"
33
29 */
30
31#include <list>
32
33#include "config/full_system.hh"
34#include "cpu/o3/rename.hh"
35
34using namespace std;
35
36template <class Impl>
36template <class Impl>
37DefaultRename<Impl>::DefaultRename(Params *params)
38 : iewToRenameDelay(params->iewToRenameDelay),
39 decodeToRenameDelay(params->decodeToRenameDelay),
40 commitToRenameDelay(params->commitToRenameDelay),
41 renameWidth(params->renameWidth),
42 commitWidth(params->commitWidth),
43 numThreads(params->numberOfThreads)
37SimpleRename<Impl>::SimpleRename(Params &params)
38 : iewToRenameDelay(params.iewToRenameDelay),
39 decodeToRenameDelay(params.decodeToRenameDelay),
40 commitToRenameDelay(params.commitToRenameDelay),
41 renameWidth(params.renameWidth),
42 commitWidth(params.commitWidth),
43 numInst(0)
44{
44{
45 _status = Inactive;
46
47 for (int i=0; i< numThreads; i++) {
48 renameStatus[i] = Idle;
49
50 freeEntries[i].iqEntries = 0;
51 freeEntries[i].lsqEntries = 0;
52 freeEntries[i].robEntries = 0;
53
54 stalls[i].iew = false;
55 stalls[i].commit = false;
56 serializeInst[i] = NULL;
57
58 instsInProgress[i] = 0;
59
60 emptyROB[i] = true;
61
62 serializeOnNextInst[i] = false;
63 }
64
65 // @todo: Make into a parameter.
66 skidBufferMax = (2 * (iewToRenameDelay * params->decodeWidth)) + renameWidth;
45 _status = Idle;
67}
68
69template <class Impl>
46}
47
48template <class Impl>
70std::string
71DefaultRename<Impl>::name() const
72{
73 return cpu->name() + ".rename";
74}
75
76template <class Impl>
77void
49void
78DefaultRename<Impl>::regStats()
50SimpleRename<Impl>::regStats()
79{
80 renameSquashCycles
51{
52 renameSquashCycles
81 .name(name() + ".RENAME:SquashCycles")
53 .name(name() + ".renameSquashCycles")
82 .desc("Number of cycles rename is squashing")
83 .prereq(renameSquashCycles);
84 renameIdleCycles
54 .desc("Number of cycles rename is squashing")
55 .prereq(renameSquashCycles);
56 renameIdleCycles
85 .name(name() + ".RENAME:IdleCycles")
57 .name(name() + ".renameIdleCycles")
86 .desc("Number of cycles rename is idle")
87 .prereq(renameIdleCycles);
88 renameBlockCycles
58 .desc("Number of cycles rename is idle")
59 .prereq(renameIdleCycles);
60 renameBlockCycles
89 .name(name() + ".RENAME:BlockCycles")
61 .name(name() + ".renameBlockCycles")
90 .desc("Number of cycles rename is blocking")
91 .prereq(renameBlockCycles);
62 .desc("Number of cycles rename is blocking")
63 .prereq(renameBlockCycles);
92 renameSerializeStallCycles
93 .name(name() + ".RENAME:serializeStallCycles")
94 .desc("count of cycles rename stalled for serializing inst")
95 .flags(Stats::total);
96 renameRunCycles
97 .name(name() + ".RENAME:RunCycles")
98 .desc("Number of cycles rename is running")
99 .prereq(renameIdleCycles);
100 renameUnblockCycles
64 renameUnblockCycles
101 .name(name() + ".RENAME:UnblockCycles")
65 .name(name() + ".renameUnblockCycles")
102 .desc("Number of cycles rename is unblocking")
103 .prereq(renameUnblockCycles);
104 renameRenamedInsts
66 .desc("Number of cycles rename is unblocking")
67 .prereq(renameUnblockCycles);
68 renameRenamedInsts
105 .name(name() + ".RENAME:RenamedInsts")
69 .name(name() + ".renameRenamedInsts")
106 .desc("Number of instructions processed by rename")
107 .prereq(renameRenamedInsts);
108 renameSquashedInsts
70 .desc("Number of instructions processed by rename")
71 .prereq(renameRenamedInsts);
72 renameSquashedInsts
109 .name(name() + ".RENAME:SquashedInsts")
73 .name(name() + ".renameSquashedInsts")
110 .desc("Number of squashed instructions processed by rename")
111 .prereq(renameSquashedInsts);
112 renameROBFullEvents
74 .desc("Number of squashed instructions processed by rename")
75 .prereq(renameSquashedInsts);
76 renameROBFullEvents
113 .name(name() + ".RENAME:ROBFullEvents")
114 .desc("Number of times rename has blocked due to ROB full")
77 .name(name() + ".renameROBFullEvents")
78 .desc("Number of times rename has considered the ROB 'full'")
115 .prereq(renameROBFullEvents);
116 renameIQFullEvents
79 .prereq(renameROBFullEvents);
80 renameIQFullEvents
117 .name(name() + ".RENAME:IQFullEvents")
118 .desc("Number of times rename has blocked due to IQ full")
81 .name(name() + ".renameIQFullEvents")
82 .desc("Number of times rename has considered the IQ 'full'")
119 .prereq(renameIQFullEvents);
83 .prereq(renameIQFullEvents);
120 renameLSQFullEvents
121 .name(name() + ".RENAME:LSQFullEvents")
122 .desc("Number of times rename has blocked due to LSQ full")
123 .prereq(renameLSQFullEvents);
124 renameFullRegistersEvents
84 renameFullRegistersEvents
125 .name(name() + ".RENAME:FullRegisterEvents")
85 .name(name() + ".renameFullRegisterEvents")
126 .desc("Number of times there has been no free registers")
127 .prereq(renameFullRegistersEvents);
128 renameRenamedOperands
86 .desc("Number of times there has been no free registers")
87 .prereq(renameFullRegistersEvents);
88 renameRenamedOperands
129 .name(name() + ".RENAME:RenamedOperands")
89 .name(name() + ".renameRenamedOperands")
130 .desc("Number of destination operands rename has renamed")
131 .prereq(renameRenamedOperands);
132 renameRenameLookups
90 .desc("Number of destination operands rename has renamed")
91 .prereq(renameRenamedOperands);
92 renameRenameLookups
133 .name(name() + ".RENAME:RenameLookups")
93 .name(name() + ".renameRenameLookups")
134 .desc("Number of register rename lookups that rename has made")
135 .prereq(renameRenameLookups);
94 .desc("Number of register rename lookups that rename has made")
95 .prereq(renameRenameLookups);
96 renameHBPlaceHolders
97 .name(name() + ".renameHBPlaceHolders")
98 .desc("Number of place holders added to the history buffer")
99 .prereq(renameHBPlaceHolders);
136 renameCommittedMaps
100 renameCommittedMaps
137 .name(name() + ".RENAME:CommittedMaps")
101 .name(name() + ".renameCommittedMaps")
138 .desc("Number of HB maps that are committed")
139 .prereq(renameCommittedMaps);
140 renameUndoneMaps
102 .desc("Number of HB maps that are committed")
103 .prereq(renameCommittedMaps);
104 renameUndoneMaps
141 .name(name() + ".RENAME:UndoneMaps")
105 .name(name() + ".renameUndoneMaps")
142 .desc("Number of HB maps that are undone due to squashing")
143 .prereq(renameUndoneMaps);
106 .desc("Number of HB maps that are undone due to squashing")
107 .prereq(renameUndoneMaps);
144 renamedSerializing
145 .name(name() + ".RENAME:serializingInsts")
146 .desc("count of serializing insts renamed")
147 .flags(Stats::total)
148 ;
149 renamedTempSerializing
150 .name(name() + ".RENAME:tempSerializingInsts")
151 .desc("count of temporary serializing insts renamed")
152 .flags(Stats::total)
153 ;
154 renameSkidInsts
155 .name(name() + ".RENAME:skidInsts")
156 .desc("count of insts added to the skid buffer")
157 .flags(Stats::total)
158 ;
108 renameValidUndoneMaps
109 .name(name() + ".renameValidUndoneMaps")
110 .desc("Number of HB maps that are undone, and are not place holders")
111 .prereq(renameValidUndoneMaps);
159}
160
161template <class Impl>
162void
112}
113
114template <class Impl>
115void
163DefaultRename<Impl>::setCPU(FullCPU *cpu_ptr)
116SimpleRename<Impl>::setCPU(FullCPU *cpu_ptr)
164{
117{
165 DPRINTF(Rename, "Setting CPU pointer.\n");
118 DPRINTF(Rename, "Rename: Setting CPU pointer.\n");
166 cpu = cpu_ptr;
167}
168
169template <class Impl>
170void
119 cpu = cpu_ptr;
120}
121
122template <class Impl>
123void
171DefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
124SimpleRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
172{
125{
173 DPRINTF(Rename, "Setting time buffer pointer.\n");
126 DPRINTF(Rename, "Rename: Setting time buffer pointer.\n");
174 timeBuffer = tb_ptr;
175
176 // Setup wire to read information from time buffer, from IEW stage.
177 fromIEW = timeBuffer->getWire(-iewToRenameDelay);
178
179 // Setup wire to read infromation from time buffer, from commit stage.
180 fromCommit = timeBuffer->getWire(-commitToRenameDelay);
181
182 // Setup wire to write information to previous stages.
183 toDecode = timeBuffer->getWire(0);
184}
185
186template <class Impl>
187void
127 timeBuffer = tb_ptr;
128
129 // Setup wire to read information from time buffer, from IEW stage.
130 fromIEW = timeBuffer->getWire(-iewToRenameDelay);
131
132 // Setup wire to read infromation from time buffer, from commit stage.
133 fromCommit = timeBuffer->getWire(-commitToRenameDelay);
134
135 // Setup wire to write information to previous stages.
136 toDecode = timeBuffer->getWire(0);
137}
138
139template <class Impl>
140void
188DefaultRename<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
141SimpleRename<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
189{
142{
190 DPRINTF(Rename, "Setting rename queue pointer.\n");
143 DPRINTF(Rename, "Rename: Setting rename queue pointer.\n");
191 renameQueue = rq_ptr;
192
193 // Setup wire to write information to future stages.
194 toIEW = renameQueue->getWire(0);
195}
196
197template <class Impl>
198void
144 renameQueue = rq_ptr;
145
146 // Setup wire to write information to future stages.
147 toIEW = renameQueue->getWire(0);
148}
149
150template <class Impl>
151void
199DefaultRename<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr)
152SimpleRename<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr)
200{
153{
201 DPRINTF(Rename, "Setting decode queue pointer.\n");
154 DPRINTF(Rename, "Rename: Setting decode queue pointer.\n");
202 decodeQueue = dq_ptr;
203
204 // Setup wire to get information from decode.
205 fromDecode = decodeQueue->getWire(-decodeToRenameDelay);
206}
207
208template <class Impl>
209void
155 decodeQueue = dq_ptr;
156
157 // Setup wire to get information from decode.
158 fromDecode = decodeQueue->getWire(-decodeToRenameDelay);
159}
160
161template <class Impl>
162void
210DefaultRename<Impl>::initStage()
163SimpleRename<Impl>::setRenameMap(RenameMap *rm_ptr)
211{
164{
212 // Grab the number of free entries directly from the stages.
213 for (int tid=0; tid < numThreads; tid++) {
214 freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid);
215 freeEntries[tid].lsqEntries = iew_ptr->ldstQueue.numFreeEntries(tid);
216 freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid);
217 emptyROB[tid] = true;
218 }
165 DPRINTF(Rename, "Rename: Setting rename map pointer.\n");
166 renameMap = rm_ptr;
219}
220
167}
168
221template<class Impl>
222void
223DefaultRename<Impl>::setActiveThreads(list<unsigned> *at_ptr)
224{
225 DPRINTF(Rename, "Setting active threads list pointer.\n");
226 activeThreads = at_ptr;
227}
228
229
230template <class Impl>
231void
169template <class Impl>
170void
232DefaultRename<Impl>::setRenameMap(RenameMap rm_ptr[])
171SimpleRename<Impl>::setFreeList(FreeList *fl_ptr)
233{
172{
234 DPRINTF(Rename, "Setting rename map pointers.\n");
235
236 for (int i=0; i<numThreads; i++) {
237 renameMap[i] = &rm_ptr[i];
238 }
239}
240
241template <class Impl>
242void
243DefaultRename<Impl>::setFreeList(FreeList *fl_ptr)
244{
245 DPRINTF(Rename, "Setting free list pointer.\n");
173 DPRINTF(Rename, "Rename: Setting free list pointer.\n");
246 freeList = fl_ptr;
247}
248
174 freeList = fl_ptr;
175}
176
249template<class Impl>
250void
251DefaultRename<Impl>::setScoreboard(Scoreboard *_scoreboard)
252{
253 DPRINTF(Rename, "Setting scoreboard pointer.\n");
254 scoreboard = _scoreboard;
255}
256
257template <class Impl>
258void
177template <class Impl>
178void
259DefaultRename<Impl>::switchOut()
179SimpleRename<Impl>::dumpHistory()
260{
180{
261 cpu->signalSwitched();
262}
181 typename list<RenameHistory>::iterator buf_it = historyBuffer.begin();
263
182
264template <class Impl>
265void
266DefaultRename<Impl>::doSwitchOut()
267{
268 for (int i = 0; i < numThreads; i++) {
269 typename list<RenameHistory>::iterator hb_it = historyBuffer[i].begin();
183 while (buf_it != historyBuffer.end())
184 {
185 cprintf("Seq num: %i\nArch reg: %i New phys reg: %i Old phys "
186 "reg: %i\n", (*buf_it).instSeqNum, (int)(*buf_it).archReg,
187 (int)(*buf_it).newPhysReg, (int)(*buf_it).prevPhysReg);
270
188
271 while (!historyBuffer[i].empty()) {
272 assert(hb_it != historyBuffer[i].end());
273
274 DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence "
275 "number %i.\n", i, (*hb_it).instSeqNum);
276
277 // Tell the rename map to set the architected register to the
278 // previous physical register that it was renamed to.
279 renameMap[i]->setEntry(hb_it->archReg, hb_it->prevPhysReg);
280
281 // Put the renamed physical register back on the free list.
282 freeList->addReg(hb_it->newPhysReg);
283
284 historyBuffer[i].erase(hb_it++);
285 }
286 insts[i].clear();
287 skidBuffer[i].clear();
189 buf_it++;
288 }
289}
290
291template <class Impl>
292void
190 }
191}
192
193template <class Impl>
194void
293DefaultRename<Impl>::takeOverFrom()
195SimpleRename<Impl>::block()
294{
196{
295 _status = Inactive;
296 initStage();
197 DPRINTF(Rename, "Rename: Blocking.\n");
198 // Set status to Blocked.
199 _status = Blocked;
297
200
298 // Reset all state prior to taking over from the other CPU.
299 for (int i=0; i< numThreads; i++) {
300 renameStatus[i] = Idle;
201 // Add the current inputs onto the skid buffer, so they can be
202 // reprocessed when this stage unblocks.
203 skidBuffer.push(*fromDecode);
301
204
302 stalls[i].iew = false;
303 stalls[i].commit = false;
304 serializeInst[i] = NULL;
305
306 instsInProgress[i] = 0;
307
308 emptyROB[i] = true;
309
310 serializeOnNextInst[i] = false;
311 }
205 // Note that this stage only signals previous stages to stall when
206 // it is the cause of the stall originates at this stage. Otherwise
207 // the previous stages are expected to check all possible stall signals.
312}
313
314template <class Impl>
208}
209
210template <class Impl>
315void
316DefaultRename<Impl>::squash(unsigned tid)
211inline void
212SimpleRename<Impl>::unblock()
317{
213{
318 DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid);
214 DPRINTF(Rename, "Rename: Read instructions out of skid buffer this "
215 "cycle.\n");
216 // Remove the now processed instructions from the skid buffer.
217 skidBuffer.pop();
319
218
320 // Clear the stall signal if rename was blocked or unblocking before.
321 // If it still needs to block, the blocking should happen the next
322 // cycle and there should be space to hold everything due to the squash.
323 if (renameStatus[tid] == Blocked ||
324 renameStatus[tid] == Unblocking ||
325 renameStatus[tid] == SerializeStall) {
326#if 0
327 // In syscall emulation, we can have both a block and a squash due
328 // to a syscall in the same cycle. This would cause both signals to
329 // be high. This shouldn't happen in full system.
330 if (toDecode->renameBlock[tid]) {
331 toDecode->renameBlock[tid] = 0;
332 } else {
333 toDecode->renameUnblock[tid] = 1;
334 }
335#else
336 toDecode->renameUnblock[tid] = 1;
337#endif
338 serializeInst[tid] = NULL;
219 // If there's still information in the skid buffer, then
220 // continue to tell previous stages to stall. They will be
221 // able to restart once the skid buffer is empty.
222 if (!skidBuffer.empty()) {
223 toDecode->renameInfo.stall = true;
224 } else {
225 DPRINTF(Rename, "Rename: Done unblocking.\n");
226 _status = Running;
339 }
227 }
340
341 // Set the status to Squashing.
342 renameStatus[tid] = Squashing;
343
344 // Squash any instructions from decode.
345 unsigned squashCount = 0;
346
347 for (int i=0; i<fromDecode->size; i++) {
348 if (fromDecode->insts[i]->threadNumber == tid) {
349 fromDecode->insts[i]->squashed = true;
350 wroteToTimeBuffer = true;
351 squashCount++;
352 }
353 }
354
355 insts[tid].clear();
356
357 // Clear the skid buffer in case it has any data in it.
358 skidBuffer[tid].clear();
359
360 doSquash(tid);
361}
362
363template <class Impl>
364void
228}
229
230template <class Impl>
231void
365DefaultRename<Impl>::tick()
232SimpleRename<Impl>::doSquash()
366{
233{
367 wroteToTimeBuffer = false;
234 typename list<RenameHistory>::iterator hb_it = historyBuffer.begin();
368
235
369 blockThisCycle = false;
236 InstSeqNum squashed_seq_num = fromCommit->commitInfo.doneSeqNum;
370
237
371 bool status_change = false;
372
373 toIEWIndex = 0;
374
375 sortInsts();
376
377 list<unsigned>::iterator threads = (*activeThreads).begin();
378
379 // Check stall and squash signals.
380 while (threads != (*activeThreads).end()) {
381 unsigned tid = *threads++;
382
383 DPRINTF(Rename, "Processing [tid:%i]\n", tid);
384
385 status_change = checkSignalsAndUpdate(tid) || status_change;
386
387 rename(status_change, tid);
388 }
389
390 if (status_change) {
391 updateStatus();
392 }
393
394 if (wroteToTimeBuffer) {
395 DPRINTF(Activity, "Activity this cycle.\n");
396 cpu->activityThisCycle();
397 }
398
399 threads = (*activeThreads).begin();
400
401 while (threads != (*activeThreads).end()) {
402 unsigned tid = *threads++;
403
404 // If we committed this cycle then doneSeqNum will be > 0
405 if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
406 !fromCommit->commitInfo[tid].squash &&
407 renameStatus[tid] != Squashing) {
408
409 removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum,
410 tid);
411 }
412 }
413
414 // @todo: make into updateProgress function
415 for (int tid=0; tid < numThreads; tid++) {
416 instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched;
417
418 assert(instsInProgress[tid] >=0);
419 }
420
421}
422
423template<class Impl>
424void
425DefaultRename<Impl>::rename(bool &status_change, unsigned tid)
426{
427 // If status is Running or idle,
428 // call renameInsts()
429 // If status is Unblocking,
430 // buffer any instructions coming from decode
431 // continue trying to empty skid buffer
432 // check if stall conditions have passed
433
434 if (renameStatus[tid] == Blocked) {
435 ++renameBlockCycles;
436 } else if (renameStatus[tid] == Squashing) {
437 ++renameSquashCycles;
438 } else if (renameStatus[tid] == SerializeStall) {
439 ++renameSerializeStallCycles;
440 }
441
442 if (renameStatus[tid] == Running ||
443 renameStatus[tid] == Idle) {
444 DPRINTF(Rename, "[tid:%u]: Not blocked, so attempting to run "
445 "stage.\n", tid);
446
447 renameInsts(tid);
448 } else if (renameStatus[tid] == Unblocking) {
449 renameInsts(tid);
450
451 if (validInsts()) {
452 // Add the current inputs to the skid buffer so they can be
453 // reprocessed when this stage unblocks.
454 skidInsert(tid);
455 }
456
457 // If we switched over to blocking, then there's a potential for
458 // an overall status change.
459 status_change = unblock(tid) || status_change || blockThisCycle;
460 }
461}
462
463template <class Impl>
464void
465DefaultRename<Impl>::renameInsts(unsigned tid)
466{
467 // Instructions can be either in the skid buffer or the queue of
468 // instructions coming from decode, depending on the status.
469 int insts_available = renameStatus[tid] == Unblocking ?
470 skidBuffer[tid].size() : insts[tid].size();
471
472 // Check the decode queue to see if instructions are available.
473 // If there are no available instructions to rename, then do nothing.
474 if (insts_available == 0) {
475 DPRINTF(Rename, "[tid:%u]: Nothing to do, breaking out early.\n",
476 tid);
477 // Should I change status to idle?
478 ++renameIdleCycles;
238#if FULL_SYSTEM
239 assert(!historyBuffer.empty());
240#else
241 // After a syscall squashes everything, the history buffer may be empty
242 // but the ROB may still be squashing instructions.
243 if (historyBuffer.empty()) {
479 return;
244 return;
480 } else if (renameStatus[tid] == Unblocking) {
481 ++renameUnblockCycles;
482 } else if (renameStatus[tid] == Running) {
483 ++renameRunCycles;
484 }
245 }
246#endif // FULL_SYSTEM
485
247
486 DynInstPtr inst;
248 // Go through the most recent instructions, undoing the mappings
249 // they did and freeing up the registers.
250 while ((*hb_it).instSeqNum > squashed_seq_num)
251 {
252 assert(hb_it != historyBuffer.end());
487
253
488 // Will have to do a different calculation for the number of free
489 // entries.
490 int free_rob_entries = calcFreeROBEntries(tid);
491 int free_iq_entries = calcFreeIQEntries(tid);
492 int free_lsq_entries = calcFreeLSQEntries(tid);
493 int min_free_entries = free_rob_entries;
254 DPRINTF(Rename, "Rename: Removing history entry with sequence "
255 "number %i.\n", (*hb_it).instSeqNum);
494
256
495 FullSource source = ROB;
257 // If it's not simply a place holder, then add the registers.
258 if (!(*hb_it).placeHolder) {
259 // Tell the rename map to set the architected register to the
260 // previous physical register that it was renamed to.
261 renameMap->setEntry(hb_it->archReg, hb_it->prevPhysReg);
496
262
497 if (free_iq_entries < min_free_entries) {
498 min_free_entries = free_iq_entries;
499 source = IQ;
500 }
263 // Put the renamed physical register back on the free list.
264 freeList->addReg(hb_it->newPhysReg);
501
265
502 if (free_lsq_entries < min_free_entries) {
503 min_free_entries = free_lsq_entries;
504 source = LSQ;
505 }
506
507 // Check if there's any space left.
508 if (min_free_entries <= 0) {
509 DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/LSQ "
510 "entries.\n"
511 "ROB has %i free entries.\n"
512 "IQ has %i free entries.\n"
513 "LSQ has %i free entries.\n",
514 tid,
515 free_rob_entries,
516 free_iq_entries,
517 free_lsq_entries);
518
519 blockThisCycle = true;
520
521 block(tid);
522
523 incrFullStat(source);
524
525 return;
526 } else if (min_free_entries < insts_available) {
527 DPRINTF(Rename, "[tid:%u]: Will have to block this cycle."
528 "%i insts available, but only %i insts can be "
529 "renamed due to ROB/IQ/LSQ limits.\n",
530 tid, insts_available, min_free_entries);
531
532 insts_available = min_free_entries;
533
534 blockThisCycle = true;
535
536 incrFullStat(source);
537 }
538
539 InstQueue &insts_to_rename = renameStatus[tid] == Unblocking ?
540 skidBuffer[tid] : insts[tid];
541
542 DPRINTF(Rename, "[tid:%u]: %i available instructions to "
543 "send iew.\n", tid, insts_available);
544
545 DPRINTF(Rename, "[tid:%u]: %i insts pipelining from Rename | %i insts "
546 "dispatched to IQ last cycle.\n",
547 tid, instsInProgress[tid], fromIEW->iewInfo[tid].dispatched);
548
549 // Handle serializing the next instruction if necessary.
550 if (serializeOnNextInst[tid]) {
551 if (emptyROB[tid] && instsInProgress[tid] == 0) {
552 // ROB already empty; no need to serialize.
553 serializeOnNextInst[tid] = false;
554 } else if (!insts_to_rename.empty()) {
555 insts_to_rename.front()->setSerializeBefore();
266 ++renameValidUndoneMaps;
556 }
267 }
557 }
558
268
559 int renamed_insts = 0;
269 historyBuffer.erase(hb_it++);
560
270
561 while (insts_available > 0 && toIEWIndex < renameWidth) {
562 DPRINTF(Rename, "[tid:%u]: Sending instructions to IEW.\n", tid);
563
564 assert(!insts_to_rename.empty());
565
566 inst = insts_to_rename.front();
567
568 insts_to_rename.pop_front();
569
570 if (renameStatus[tid] == Unblocking) {
571 DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%#x from rename "
572 "skidBuffer\n",
573 tid, inst->seqNum, inst->readPC());
574 }
575
576 if (inst->isSquashed()) {
577 DPRINTF(Rename, "[tid:%u]: instruction %i with PC %#x is "
578 "squashed, skipping.\n",
579 tid, inst->seqNum, inst->threadNumber,inst->readPC());
580
581 ++renameSquashedInsts;
582
583 // Decrement how many instructions are available.
584 --insts_available;
585
586 continue;
587 }
588
589 DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with "
590 "PC %#x.\n",
591 tid, inst->seqNum, inst->readPC());
592
593 // Handle serializeAfter/serializeBefore instructions.
594 // serializeAfter marks the next instruction as serializeBefore.
595 // serializeBefore makes the instruction wait in rename until the ROB
596 // is empty.
597
598 // In this model, IPR accesses are serialize before
599 // instructions, and store conditionals are serialize after
600 // instructions. This is mainly due to lack of support for
601 // out-of-order operations of either of those classes of
602 // instructions.
603 if ((inst->isIprAccess() || inst->isSerializeBefore()) &&
604 !inst->isSerializeHandled()) {
605 DPRINTF(Rename, "Serialize before instruction encountered.\n");
606
607 if (!inst->isTempSerializeBefore()) {
608 renamedSerializing++;
609 inst->setSerializeHandled();
610 } else {
611 renamedTempSerializing++;
612 }
613
614 // Change status over to SerializeStall so that other stages know
615 // what this is blocked on.
616 renameStatus[tid] = SerializeStall;
617
618 serializeInst[tid] = inst;
619
620 blockThisCycle = true;
621
622 break;
623 } else if ((inst->isStoreConditional() || inst->isSerializeAfter()) &&
624 !inst->isSerializeHandled()) {
625 DPRINTF(Rename, "Serialize after instruction encountered.\n");
626
627 renamedSerializing++;
628
629 inst->setSerializeHandled();
630
631 serializeAfter(insts_to_rename, tid);
632 }
633
634 // Check here to make sure there are enough destination registers
635 // to rename to. Otherwise block.
636 if (renameMap[tid]->numFreeEntries() < inst->numDestRegs()) {
637 DPRINTF(Rename, "Blocking due to lack of free "
638 "physical registers to rename to.\n");
639 blockThisCycle = true;
640
641 ++renameFullRegistersEvents;
642
643 break;
644 }
645
646 renameSrcRegs(inst, inst->threadNumber);
647
648 renameDestRegs(inst, inst->threadNumber);
649
650 ++renamed_insts;
651
652 // Put instruction in rename queue.
653 toIEW->insts[toIEWIndex] = inst;
654 ++(toIEW->size);
655
656 // Increment which instruction we're on.
657 ++toIEWIndex;
658
659 // Decrement how many instructions are available.
660 --insts_available;
271 ++renameUndoneMaps;
661 }
272 }
662
663 instsInProgress[tid] += renamed_insts;
664 renameRenamedInsts += renamed_insts;
665
666 // If we wrote to the time buffer, record this.
667 if (toIEWIndex) {
668 wroteToTimeBuffer = true;
669 }
670
671 // Check if there's any instructions left that haven't yet been renamed.
672 // If so then block.
673 if (insts_available) {
674 blockThisCycle = true;
675 }
676
677 if (blockThisCycle) {
678 block(tid);
679 toDecode->renameUnblock[tid] = false;
680 }
681}
682
273}
274
683template<class Impl>
684void
685DefaultRename<Impl>::skidInsert(unsigned tid)
686{
687 DynInstPtr inst = NULL;
688
689 while (!insts[tid].empty()) {
690 inst = insts[tid].front();
691
692 insts[tid].pop_front();
693
694 assert(tid == inst->threadNumber);
695
696 DPRINTF(Rename, "[tid:%u]: Inserting [sn:%lli] PC:%#x into Rename "
697 "skidBuffer\n", tid, inst->seqNum, inst->readPC());
698
699 ++renameSkidInsts;
700
701 skidBuffer[tid].push_back(inst);
702 }
703
704 if (skidBuffer[tid].size() > skidBufferMax)
705 panic("Skidbuffer Exceeded Max Size");
706}
707
708template <class Impl>
709void
275template <class Impl>
276void
710DefaultRename<Impl>::sortInsts()
277SimpleRename<Impl>::squash()
711{
278{
712 int insts_from_decode = fromDecode->size;
713#ifdef DEBUG
714 for (int i=0; i < numThreads; i++)
715 assert(insts[i].empty());
716#endif
717 for (int i = 0; i < insts_from_decode; ++i) {
718 DynInstPtr inst = fromDecode->insts[i];
719 insts[inst->threadNumber].push_back(inst);
720 }
721}
279 DPRINTF(Rename, "Rename: Squashing instructions.\n");
280 // Set the status to Squashing.
281 _status = Squashing;
722
282
723template<class Impl>
724bool
725DefaultRename<Impl>::skidsEmpty()
726{
727 list<unsigned>::iterator threads = (*activeThreads).begin();
283 numInst = 0;
728
284
729 while (threads != (*activeThreads).end()) {
730 if (!skidBuffer[*threads++].empty())
731 return false;
285 // Clear the skid buffer in case it has any data in it.
286 while (!skidBuffer.empty())
287 {
288 skidBuffer.pop();
732 }
733
289 }
290
734 return true;
291 doSquash();
735}
736
737template<class Impl>
738void
292}
293
294template<class Impl>
295void
739DefaultRename<Impl>::updateStatus()
296SimpleRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num)
740{
297{
741 bool any_unblocking = false;
298 DPRINTF(Rename, "Rename: Removing a committed instruction from the "
299 "history buffer, until sequence number %lli.\n", inst_seq_num);
300 typename list<RenameHistory>::iterator hb_it = historyBuffer.end();
742
301
743 list<unsigned>::iterator threads = (*activeThreads).begin();
302 --hb_it;
744
303
745 threads = (*activeThreads).begin();
746
747 while (threads != (*activeThreads).end()) {
748 unsigned tid = *threads++;
749
750 if (renameStatus[tid] == Unblocking) {
751 any_unblocking = true;
752 break;
753 }
304 if (hb_it->instSeqNum > inst_seq_num) {
305 DPRINTF(Rename, "Rename: Old sequence number encountered. Ensure "
306 "that a syscall happened recently.\n");
307 return;
754 }
755
308 }
309
756 // Rename will have activity if it's unblocking.
757 if (any_unblocking) {
758 if (_status == Inactive) {
759 _status = Active;
310 while ((*hb_it).instSeqNum != inst_seq_num)
311 {
312 // Make sure we haven't gone off the end of the list.
313 assert(hb_it != historyBuffer.end());
760
314
761 DPRINTF(Activity, "Activating stage.\n");
315 // In theory instructions at the end of the history buffer
316 // should be older than the instruction being removed, which
317 // means they will have a lower sequence number. Also the
318 // instruction being removed from the history really should
319 // be the last instruction in the list, as it is the instruction
320 // that was just committed that is being removed.
321 assert(hb_it->instSeqNum < inst_seq_num);
322 DPRINTF(Rename, "Rename: Freeing up older rename of reg %i, sequence"
323 " number %i.\n",
324 (*hb_it).prevPhysReg, (*hb_it).instSeqNum);
762
325
763 cpu->activateStage(FullCPU::RenameIdx);
326 if (!(*hb_it).placeHolder) {
327 freeList->addReg((*hb_it).prevPhysReg);
328 ++renameCommittedMaps;
764 }
329 }
765 } else {
766 // If it's not unblocking, then rename will not have any internal
767 // activity. Switch it to inactive.
768 if (_status == Active) {
769 _status = Inactive;
770 DPRINTF(Activity, "Deactivating stage.\n");
771
330
772 cpu->deactivateStage(FullCPU::RenameIdx);
773 }
331 historyBuffer.erase(hb_it--);
774 }
332 }
775}
776
333
777template <class Impl>
778bool
779DefaultRename<Impl>::block(unsigned tid)
780{
781 DPRINTF(Rename, "[tid:%u]: Blocking.\n", tid);
782
783 // Add the current inputs onto the skid buffer, so they can be
784 // reprocessed when this stage unblocks.
785 skidInsert(tid);
786
787 // Only signal backwards to block if the previous stages do not think
788 // rename is already blocked.
789 if (renameStatus[tid] != Blocked) {
790 if (renameStatus[tid] != Unblocking) {
791 toDecode->renameBlock[tid] = true;
792 toDecode->renameUnblock[tid] = false;
793 wroteToTimeBuffer = true;
794 }
795
796 // Rename can not go from SerializeStall to Blocked, otherwise
797 // it would not know to complete the serialize stall.
798 if (renameStatus[tid] != SerializeStall) {
799 // Set status to Blocked.
800 renameStatus[tid] = Blocked;
801 return true;
802 }
334 // Finally free up the previous register of the finished instruction
335 // itself.
336 if (!(*hb_it).placeHolder) {
337 freeList->addReg(hb_it->prevPhysReg);
338 ++renameCommittedMaps;
803 }
804
339 }
340
805 return false;
341 historyBuffer.erase(hb_it);
806}
807
808template <class Impl>
342}
343
344template <class Impl>
809bool
810DefaultRename<Impl>::unblock(unsigned tid)
811{
812 DPRINTF(Rename, "[tid:%u]: Trying to unblock.\n", tid);
813
814 // Rename is done unblocking if the skid buffer is empty.
815 if (skidBuffer[tid].empty() && renameStatus[tid] != SerializeStall) {
816
817 DPRINTF(Rename, "[tid:%u]: Done unblocking.\n", tid);
818
819 toDecode->renameUnblock[tid] = true;
820 wroteToTimeBuffer = true;
821
822 renameStatus[tid] = Running;
823 return true;
824 }
825
826 return false;
827}
828
829template <class Impl>
830void
831DefaultRename<Impl>::doSquash(unsigned tid)
832{
833 typename list<RenameHistory>::iterator hb_it = historyBuffer[tid].begin();
834
835 InstSeqNum squashed_seq_num = fromCommit->commitInfo[tid].doneSeqNum;
836
837 // After a syscall squashes everything, the history buffer may be empty
838 // but the ROB may still be squashing instructions.
839 if (historyBuffer[tid].empty()) {
840 return;
841 }
842
843 // Go through the most recent instructions, undoing the mappings
844 // they did and freeing up the registers.
845 while (!historyBuffer[tid].empty() &&
846 (*hb_it).instSeqNum > squashed_seq_num) {
847 assert(hb_it != historyBuffer[tid].end());
848
849 DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence "
850 "number %i.\n", tid, (*hb_it).instSeqNum);
851
852 // Tell the rename map to set the architected register to the
853 // previous physical register that it was renamed to.
854 renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg);
855
856 // Put the renamed physical register back on the free list.
857 freeList->addReg(hb_it->newPhysReg);
858
859 historyBuffer[tid].erase(hb_it++);
860
861 ++renameUndoneMaps;
862 }
863}
864
865template<class Impl>
866void
867DefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, unsigned tid)
868{
869 DPRINTF(Rename, "[tid:%u]: Removing a committed instruction from the "
870 "history buffer %u (size=%i), until [sn:%lli].\n",
871 tid, tid, historyBuffer[tid].size(), inst_seq_num);
872
873 typename list<RenameHistory>::iterator hb_it = historyBuffer[tid].end();
874
875 --hb_it;
876
877 if (historyBuffer[tid].empty()) {
878 DPRINTF(Rename, "[tid:%u]: History buffer is empty.\n", tid);
879 return;
880 } else if (hb_it->instSeqNum > inst_seq_num) {
881 DPRINTF(Rename, "[tid:%u]: Old sequence number encountered. Ensure "
882 "that a syscall happened recently.\n", tid);
883 return;
884 }
885
886 // Commit all the renames up until (and including) the committed sequence
887 // number. Some or even all of the committed instructions may not have
888 // rename histories if they did not have destination registers that were
889 // renamed.
890 while (!historyBuffer[tid].empty() &&
891 hb_it != historyBuffer[tid].end() &&
892 (*hb_it).instSeqNum <= inst_seq_num) {
893
894 DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i, "
895 "[sn:%lli].\n",
896 tid, (*hb_it).prevPhysReg, (*hb_it).instSeqNum);
897
898 freeList->addReg((*hb_it).prevPhysReg);
899 ++renameCommittedMaps;
900
901 historyBuffer[tid].erase(hb_it--);
902 }
903}
904
905template <class Impl>
906inline void
345inline void
907DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst,unsigned tid)
346SimpleRename<Impl>::renameSrcRegs(DynInstPtr &inst)
908{
347{
909 assert(renameMap[tid] != 0);
910
911 unsigned num_src_regs = inst->numSrcRegs();
912
913 // Get the architectual register numbers from the source and
914 // destination operands, and redirect them to the right register.
915 // Will need to mark dependencies though.
348 unsigned num_src_regs = inst->numSrcRegs();
349
350 // Get the architectual register numbers from the source and
351 // destination operands, and redirect them to the right register.
352 // Will need to mark dependencies though.
916 for (int src_idx = 0; src_idx < num_src_regs; src_idx++) {
353 for (int src_idx = 0; src_idx < num_src_regs; src_idx++)
354 {
917 RegIndex src_reg = inst->srcRegIdx(src_idx);
918
919 // Look up the source registers to get the phys. register they've
920 // been renamed to, and set the sources to those registers.
355 RegIndex src_reg = inst->srcRegIdx(src_idx);
356
357 // Look up the source registers to get the phys. register they've
358 // been renamed to, and set the sources to those registers.
921 PhysRegIndex renamed_reg = renameMap[tid]->lookup(src_reg);
359 PhysRegIndex renamed_reg = renameMap->lookup(src_reg);
922
360
923 DPRINTF(Rename, "[tid:%u]: Looking up arch reg %i, got "
924 "physical reg %i.\n", tid, (int)src_reg,
925 (int)renamed_reg);
361 DPRINTF(Rename, "Rename: Looking up arch reg %i, got "
362 "physical reg %i.\n", (int)src_reg, (int)renamed_reg);
926
927 inst->renameSrcReg(src_idx, renamed_reg);
928
363
364 inst->renameSrcReg(src_idx, renamed_reg);
365
929 // See if the register is ready or not.
930 if (scoreboard->getReg(renamed_reg) == true) {
931 DPRINTF(Rename, "[tid:%u]: Register is ready.\n", tid);
366 // Either incorporate it into the info passed back,
367 // or make another function call to see if that register is
368 // ready or not.
369 if (renameMap->isReady(renamed_reg)) {
370 DPRINTF(Rename, "Rename: Register is ready.\n");
932
933 inst->markSrcRegReady(src_idx);
934 }
935
936 ++renameRenameLookups;
937 }
938}
939
940template <class Impl>
941inline void
371
372 inst->markSrcRegReady(src_idx);
373 }
374
375 ++renameRenameLookups;
376 }
377}
378
379template <class Impl>
380inline void
942DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst,unsigned tid)
381SimpleRename<Impl>::renameDestRegs(DynInstPtr &inst)
943{
382{
944 typename RenameMap::RenameInfo rename_result;
383 typename SimpleRenameMap::RenameInfo rename_result;
945
946 unsigned num_dest_regs = inst->numDestRegs();
947
384
385 unsigned num_dest_regs = inst->numDestRegs();
386
948 // Rename the destination registers.
949 for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) {
950 RegIndex dest_reg = inst->destRegIdx(dest_idx);
387 // If it's an instruction with no destination registers, then put
388 // a placeholder within the history buffer. It might be better
389 // to not put it in the history buffer at all (other than branches,
390 // which always need at least a place holder), and differentiate
391 // between instructions with and without destination registers
392 // when getting from commit the instructions that committed.
393 if (num_dest_regs == 0) {
394 RenameHistory hb_entry(inst->seqNum);
951
395
952 // Get the physical register that the destination will be
953 // renamed to.
954 rename_result = renameMap[tid]->rename(dest_reg);
396 historyBuffer.push_front(hb_entry);
955
397
956 //Mark Scoreboard entry as not ready
957 scoreboard->unsetReg(rename_result.first);
398 DPRINTF(Rename, "Rename: Adding placeholder instruction to "
399 "history buffer, sequence number %lli.\n",
400 inst->seqNum);
958
401
959 DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical "
960 "reg %i.\n", tid, (int)dest_reg,
961 (int)rename_result.first);
402 ++renameHBPlaceHolders;
403 } else {
962
404
963 // Record the rename information so that a history can be kept.
964 RenameHistory hb_entry(inst->seqNum, dest_reg,
965 rename_result.first,
966 rename_result.second);
405 // Rename the destination registers.
406 for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++)
407 {
408 RegIndex dest_reg = inst->destRegIdx(dest_idx);
967
409
968 historyBuffer[tid].push_front(hb_entry);
410 // Get the physical register that the destination will be
411 // renamed to.
412 rename_result = renameMap->rename(dest_reg);
969
413
970 DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer, "
971 "[sn:%lli].\n",tid,
972 (*historyBuffer[tid].begin()).instSeqNum);
414 DPRINTF(Rename, "Rename: Renaming arch reg %i to physical "
415 "reg %i.\n", (int)dest_reg,
416 (int)rename_result.first);
973
417
974 // Tell the instruction to rename the appropriate destination
975 // register (dest_idx) to the new physical register
976 // (rename_result.first), and record the previous physical
977 // register that the same logical register was renamed to
978 // (rename_result.second).
979 inst->renameDestReg(dest_idx,
980 rename_result.first,
981 rename_result.second);
418 // Record the rename information so that a history can be kept.
419 RenameHistory hb_entry(inst->seqNum, dest_reg,
420 rename_result.first,
421 rename_result.second);
982
422
983 ++renameRenamedOperands;
423 historyBuffer.push_front(hb_entry);
424
425 DPRINTF(Rename, "Rename: Adding instruction to history buffer, "
426 "sequence number %lli.\n",
427 (*historyBuffer.begin()).instSeqNum);
428
429 // Tell the instruction to rename the appropriate destination
430 // register (dest_idx) to the new physical register
431 // (rename_result.first), and record the previous physical
432 // register that the same logical register was renamed to
433 // (rename_result.second).
434 inst->renameDestReg(dest_idx,
435 rename_result.first,
436 rename_result.second);
437
438 ++renameRenamedOperands;
439 }
984 }
985}
986
987template <class Impl>
988inline int
440 }
441}
442
443template <class Impl>
444inline int
989DefaultRename<Impl>::calcFreeROBEntries(unsigned tid)
445SimpleRename<Impl>::calcFreeROBEntries()
990{
446{
991 int num_free = freeEntries[tid].robEntries -
992 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched);
993
994 //DPRINTF(Rename,"[tid:%i]: %i rob free\n",tid,num_free);
995
996 return num_free;
447 return fromCommit->commitInfo.freeROBEntries -
448 renameWidth * iewToRenameDelay;
997}
998
999template <class Impl>
1000inline int
449}
450
451template <class Impl>
452inline int
1001DefaultRename<Impl>::calcFreeIQEntries(unsigned tid)
453SimpleRename<Impl>::calcFreeIQEntries()
1002{
454{
1003 int num_free = freeEntries[tid].iqEntries -
1004 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched);
1005
1006 //DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free);
1007
1008 return num_free;
455 return fromIEW->iewInfo.freeIQEntries - renameWidth * iewToRenameDelay;
1009}
1010
456}
457
1011template <class Impl>
1012inline int
1013DefaultRename<Impl>::calcFreeLSQEntries(unsigned tid)
458template
459void
460SimpleRename<Impl>::tick()
1014{
461{
1015 int num_free = freeEntries[tid].lsqEntries -
1016 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLSQ);
462 // Rename will need to try to rename as many instructions as it
463 // has bandwidth, unless it is blocked.
1017
464
1018 //DPRINTF(Rename,"[tid:%i]: %i lsq free\n",tid,num_free);
465 // Check if _status is BarrierStall. If so, then check if the number
466 // of free ROB entries is equal to the number of total ROB entries.
467 // Once equal then wake this stage up. Set status to unblocking maybe.
1019
468
1020 return num_free;
1021}
469 if (_status != Blocked && _status != Squashing) {
470 DPRINTF(Rename, "Rename: Status is not blocked, will attempt to "
471 "run stage.\n");
472 // Make sure that the skid buffer has something in it if the
473 // status is unblocking.
474 assert(_status == Unblocking ? !skidBuffer.empty() : 1);
1022
475
1023template <class Impl>
1024unsigned
1025DefaultRename<Impl>::validInsts()
1026{
1027 unsigned inst_count = 0;
476 rename();
1028
477
1029 for (int i=0; i<fromDecode->size; i++) {
1030 if (!fromDecode->insts[i]->squashed)
1031 inst_count++;
1032 }
478 // If the status was unblocking, then instructions from the skid
479 // buffer were used. Remove those instructions and handle
480 // the rest of unblocking.
481 if (_status == Unblocking) {
482 ++renameUnblockCycles;
1033
483
1034 return inst_count;
1035}
484 if (fromDecode->size > 0) {
485 // Add the current inputs onto the skid buffer, so they can be
486 // reprocessed when this stage unblocks.
487 skidBuffer.push(*fromDecode);
488 }
1036
489
1037template <class Impl>
1038void
1039DefaultRename<Impl>::readStallSignals(unsigned tid)
1040{
1041 if (fromIEW->iewBlock[tid]) {
1042 stalls[tid].iew = true;
1043 }
490 unblock();
491 }
492 } else if (_status == Blocked) {
493 ++renameBlockCycles;
1044
494
1045 if (fromIEW->iewUnblock[tid]) {
1046 assert(stalls[tid].iew);
1047 stalls[tid].iew = false;
1048 }
495 // If stage is blocked and still receiving valid instructions,
496 // make sure to store them in the skid buffer.
497 if (fromDecode->size > 0) {
1049
498
1050 if (fromCommit->commitBlock[tid]) {
1051 stalls[tid].commit = true;
1052 }
499 block();
1053
500
1054 if (fromCommit->commitUnblock[tid]) {
1055 assert(stalls[tid].commit);
1056 stalls[tid].commit = false;
1057 }
1058}
501 // Continue to tell previous stage to stall.
502 toDecode->renameInfo.stall = true;
503 }
1059
504
1060template <class Impl>
1061bool
1062DefaultRename<Impl>::checkStall(unsigned tid)
1063{
1064 bool ret_val = false;
505 if (!fromIEW->iewInfo.stall &&
506 !fromCommit->commitInfo.stall &&
507 calcFreeROBEntries() > 0 &&
508 calcFreeIQEntries() > 0 &&
509 renameMap->numFreeEntries() > 0) {
1065
510
1066 if (stalls[tid].iew) {
1067 DPRINTF(Rename,"[tid:%i]: Stall from IEW stage detected.\n", tid);
1068 ret_val = true;
1069 } else if (stalls[tid].commit) {
1070 DPRINTF(Rename,"[tid:%i]: Stall from Commit stage detected.\n", tid);
1071 ret_val = true;
1072 } else if (calcFreeROBEntries(tid) <= 0) {
1073 DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid);
1074 ret_val = true;
1075 } else if (calcFreeIQEntries(tid) <= 0) {
1076 DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid);
1077 ret_val = true;
1078 } else if (calcFreeLSQEntries(tid) <= 0) {
1079 DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid);
1080 ret_val = true;
1081 } else if (renameMap[tid]->numFreeEntries() <= 0) {
1082 DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n", tid);
1083 ret_val = true;
1084 } else if (renameStatus[tid] == SerializeStall &&
1085 (!emptyROB[tid] || instsInProgress[tid])) {
1086 DPRINTF(Rename,"[tid:%i]: Stall: Serialize stall and ROB is not "
1087 "empty.\n",
1088 tid);
1089 ret_val = true;
511 // Need to be sure to check all blocking conditions above.
512 // If they have cleared, then start unblocking.
513 DPRINTF(Rename, "Rename: Stall signals cleared, going to "
514 "unblock.\n");
515 _status = Unblocking;
516
517 // Continue to tell previous stage to block until this stage
518 // is done unblocking.
519 toDecode->renameInfo.stall = true;
520 } else {
521 // Otherwise no conditions have changed. Tell previous
522 // stage to continue blocking.
523 toDecode->renameInfo.stall = true;
524 }
525
526 if (fromCommit->commitInfo.squash ||
527 fromCommit->commitInfo.robSquashing) {
528 squash();
529 return;
530 }
531 } else if (_status == Squashing) {
532 ++renameSquashCycles;
533
534 if (fromCommit->commitInfo.squash) {
535 squash();
536 } else if (!fromCommit->commitInfo.squash &&
537 !fromCommit->commitInfo.robSquashing) {
538
539 DPRINTF(Rename, "Rename: Done squashing, going to running.\n");
540 _status = Running;
541 rename();
542 } else {
543 doSquash();
544 }
1090 }
1091
545 }
546
1092 return ret_val;
547 // Ugly code, revamp all of the tick() functions eventually.
548 if (fromCommit->commitInfo.doneSeqNum != 0 && _status != Squashing) {
549#if !FULL_SYSTEM
550 if (!fromCommit->commitInfo.squash) {
551 removeFromHistory(fromCommit->commitInfo.doneSeqNum);
552 }
553#else
554 removeFromHistory(fromCommit->commitInfo.doneSeqNum);
555#endif
556 }
557
1093}
1094
558}
559
1095template <class Impl>
560template
1096void
561void
1097DefaultRename<Impl>::readFreeEntries(unsigned tid)
562SimpleRename<Impl>::rename()
1098{
563{
1099 bool updated = false;
1100 if (fromIEW->iewInfo[tid].usedIQ) {
1101 freeEntries[tid].iqEntries =
1102 fromIEW->iewInfo[tid].freeIQEntries;
1103 updated = true;
564 // Check if any of the stages ahead of rename are telling rename
565 // to squash. The squash() function will also take care of fixing up
566 // the rename map and the free list.
567 if (fromCommit->commitInfo.squash ||
568 fromCommit->commitInfo.robSquashing) {
569 DPRINTF(Rename, "Rename: Receiving signal from Commit to squash.\n");
570 squash();
571 return;
1104 }
1105
572 }
573
1106 if (fromIEW->iewInfo[tid].usedLSQ) {
1107 freeEntries[tid].lsqEntries =
1108 fromIEW->iewInfo[tid].freeLSQEntries;
1109 updated = true;
574 // Check if time buffer is telling this stage to stall.
575 if (fromIEW->iewInfo.stall ||
576 fromCommit->commitInfo.stall) {
577 DPRINTF(Rename, "Rename: Receiving signal from IEW/Commit to "
578 "stall.\n");
579 block();
580 return;
1110 }
1111
581 }
582
1112 if (fromCommit->commitInfo[tid].usedROB) {
1113 freeEntries[tid].robEntries =
1114 fromCommit->commitInfo[tid].freeROBEntries;
1115 emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB;
1116 updated = true;
583 // Check if the current status is squashing. If so, set its status
584 // to running and resume execution the next cycle.
585 if (_status == Squashing) {
586 DPRINTF(Rename, "Rename: Done squashing.\n");
587 _status = Running;
588 return;
1117 }
1118
589 }
590
1119 DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, Free LSQ: %i\n",
1120 tid,
1121 freeEntries[tid].iqEntries,
1122 freeEntries[tid].robEntries,
1123 freeEntries[tid].lsqEntries);
591 // Check the decode queue to see if instructions are available.
592 // If there are no available instructions to rename, then do nothing.
593 // Or, if the stage is currently unblocking, then go ahead and run it.
594 if (fromDecode->size == 0 && _status != Unblocking) {
595 DPRINTF(Rename, "Rename: Nothing to do, breaking out early.\n");
596 // Should I change status to idle?
597 return;
598 }
1124
599
1125 DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n",
1126 tid, instsInProgress[tid]);
1127}
600 ////////////////////////////////////
601 // Actual rename part.
602 ////////////////////////////////////
1128
603
1129template <class Impl>
1130bool
1131DefaultRename<Impl>::checkSignalsAndUpdate(unsigned tid)
1132{
1133 // Check if there's a squash signal, squash if there is
1134 // Check stall signals, block if necessary.
1135 // If status was blocked
1136 // check if stall conditions have passed
1137 // if so then go to unblocking
1138 // If status was Squashing
1139 // check if squashing is not high. Switch to running this cycle.
1140 // If status was serialize stall
1141 // check if ROB is empty and no insts are in flight to the ROB
604 DynInstPtr inst;
1142
605
1143 readFreeEntries(tid);
1144 readStallSignals(tid);
606 // If we're unblocking, then we may be in the middle of an instruction
607 // group. Subtract off numInst to get the proper number of instructions
608 // left.
609 int insts_available = _status == Unblocking ?
610 skidBuffer.front().size - numInst :
611 fromDecode->size;
1145
612
1146 if (fromCommit->commitInfo[tid].squash) {
1147 DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from "
1148 "commit.\n", tid);
613 bool block_this_cycle = false;
1149
614
1150 squash(tid);
615 // Will have to do a different calculation for the number of free
616 // entries. Number of free entries recorded on this cycle -
617 // renameWidth * renameToDecodeDelay
618 int free_rob_entries = calcFreeROBEntries();
619 int free_iq_entries = calcFreeIQEntries();
620 int min_iq_rob = min(free_rob_entries, free_iq_entries);
1151
621
1152 return true;
1153 }
622 unsigned to_iew_index = 0;
1154
623
1155 if (fromCommit->commitInfo[tid].robSquashing) {
1156 DPRINTF(Rename, "[tid:%u]: ROB is still squashing.\n", tid);
624 // Check if there's any space left.
625 if (min_iq_rob <= 0) {
626 DPRINTF(Rename, "Rename: Blocking due to no free ROB or IQ "
627 "entries.\n"
628 "Rename: ROB has %d free entries.\n"
629 "Rename: IQ has %d free entries.\n",
630 free_rob_entries,
631 free_iq_entries);
632 block();
633 // Tell previous stage to stall.
634 toDecode->renameInfo.stall = true;
1157
635
1158 renameStatus[tid] = Squashing;
636 if (free_rob_entries <= 0) {
637 ++renameROBFullEvents;
638 } else {
639 ++renameIQFullEvents;
640 }
1159
641
1160 return true;
1161 }
642 return;
643 } else if (min_iq_rob < insts_available) {
644 DPRINTF(Rename, "Rename: Will have to block this cycle. Only "
645 "%i insts can be renamed due to IQ/ROB limits.\n",
646 min_iq_rob);
1162
647
1163 if (checkStall(tid)) {
1164 return block(tid);
1165 }
648 insts_available = min_iq_rob;
1166
649
1167 if (renameStatus[tid] == Blocked) {
1168 DPRINTF(Rename, "[tid:%u]: Done blocking, switching to unblocking.\n",
1169 tid);
650 block_this_cycle = true;
1170
651
1171 renameStatus[tid] = Unblocking;
652 if (free_rob_entries < free_iq_entries) {
653 ++renameROBFullEvents;
654 } else {
655 ++renameIQFullEvents;
656 }
657 }
1172
658
1173 unblock(tid);
659 while (insts_available > 0) {
660 DPRINTF(Rename, "Rename: Sending instructions to iew.\n");
1174
661
1175 return true;
1176 }
662 // Get the next instruction either from the skid buffer or the
663 // decode queue.
664 inst = _status == Unblocking ? skidBuffer.front().insts[numInst] :
665 fromDecode->insts[numInst];
1177
666
1178 if (renameStatus[tid] == Squashing) {
1179 // Switch status to running if rename isn't being told to block or
1180 // squash this cycle.
1181 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n",
1182 tid);
667 if (inst->isSquashed()) {
668 DPRINTF(Rename, "Rename: instruction %i with PC %#x is "
669 "squashed, skipping.\n",
670 inst->seqNum, inst->readPC());
1183
671
1184 renameStatus[tid] = Running;
672 // Go to the next instruction.
673 ++numInst;
1185
674
1186 return false;
1187 }
675 ++renameSquashedInsts;
1188
676
1189 if (renameStatus[tid] == SerializeStall) {
1190 // Stall ends once the ROB is free.
1191 DPRINTF(Rename, "[tid:%u]: Done with serialize stall, switching to "
1192 "unblocking.\n", tid);
677 // Decrement how many instructions are available.
678 --insts_available;
1193
679
1194 DynInstPtr serial_inst = serializeInst[tid];
680 continue;
681 }
1195
682
1196 renameStatus[tid] = Unblocking;
683 DPRINTF(Rename, "Rename: Processing instruction %i with PC %#x.\n",
684 inst->seqNum, inst->readPC());
1197
685
1198 unblock(tid);
686 // If it's a trap instruction, then it needs to wait here within
687 // rename until the ROB is empty. Needs a way to detect that the
688 // ROB is empty. Maybe an event?
689 // Would be nice if it could be avoided putting this into a
690 // specific stage and instead just put it into the AlphaFullCPU.
691 // Might not really be feasible though...
692 // (EXCB, TRAPB)
693 if (inst->isSerializing()) {
694 panic("Rename: Serializing instruction encountered.\n");
695 DPRINTF(Rename, "Rename: Serializing instruction "
696 "encountered.\n");
1199
697
1200 DPRINTF(Rename, "[tid:%u]: Processing instruction [%lli] with "
1201 "PC %#x.\n",
1202 tid, serial_inst->seqNum, serial_inst->readPC());
698 // Change status over to BarrierStall so that other stages know
699 // what this is blocked on.
700 _status = BarrierStall;
1203
701
1204 // Put instruction into queue here.
1205 serial_inst->clearSerializeBefore();
702 block_this_cycle = true;
1206
703
1207 if (!skidBuffer[tid].empty()) {
1208 skidBuffer[tid].push_front(serial_inst);
1209 } else {
1210 insts[tid].push_front(serial_inst);
704 break;
1211 }
1212
705 }
706
1213 DPRINTF(Rename, "[tid:%u]: Instruction must be processed by rename."
1214 " Adding to front of list.", tid);
707 // Check here to make sure there are enough destination registers
708 // to rename to. Otherwise block.
709 if (renameMap->numFreeEntries() < inst->numDestRegs())
710 {
711 DPRINTF(Rename, "Rename: Blocking due to lack of free "
712 "physical registers to rename to.\n");
713 // Need some sort of event based on a register being freed.
1215
714
1216 serializeInst[tid] = NULL;
715 block_this_cycle = true;
1217
716
1218 return true;
1219 }
717 ++renameFullRegistersEvents;
1220
718
1221 // If we've reached this point, we have not gotten any signals that
1222 // cause rename to change its status. Rename remains the same as before.
1223 return false;
1224}
719 break;
720 }
1225
721
1226template<class Impl>
1227void
1228DefaultRename<Impl>::serializeAfter(InstQueue &inst_list,
1229 unsigned tid)
1230{
1231 if (inst_list.empty()) {
1232 // Mark a bit to say that I must serialize on the next instruction.
1233 serializeOnNextInst[tid] = true;
1234 return;
1235 }
722 renameSrcRegs(inst);
1236
723
1237 // Set the next instruction as serializing.
1238 inst_list.front()->setSerializeBefore();
1239}
724 renameDestRegs(inst);
1240
725
1241template <class Impl>
1242inline void
1243DefaultRename<Impl>::incrFullStat(const FullSource &source)
1244{
1245 switch (source) {
1246 case ROB:
1247 ++renameROBFullEvents;
1248 break;
1249 case IQ:
1250 ++renameIQFullEvents;
1251 break;
1252 case LSQ:
1253 ++renameLSQFullEvents;
1254 break;
1255 default:
1256 panic("Rename full stall stat should be incremented for a reason!");
1257 break;
1258 }
1259}
726 // Put instruction in rename queue.
727 toIEW->insts[to_iew_index] = inst;
728 ++(toIEW->size);
1260
729
1261template <class Impl>
1262void
1263DefaultRename<Impl>::dumpHistory()
1264{
1265 typename list<RenameHistory>::iterator buf_it;
730 // Decrease the number of free ROB and IQ entries.
731 --free_rob_entries;
732 --free_iq_entries;
1266
733
1267 for (int i = 0; i < numThreads; i++) {
734 // Increment which instruction we're on.
735 ++to_iew_index;
736 ++numInst;
1268
737
1269 buf_it = historyBuffer[i].begin();
738 ++renameRenamedInsts;
1270
739
1271 while (buf_it != historyBuffer[i].end()) {
1272 cprintf("Seq num: %i\nArch reg: %i New phys reg: %i Old phys "
1273 "reg: %i\n", (*buf_it).instSeqNum, (int)(*buf_it).archReg,
1274 (int)(*buf_it).newPhysReg, (int)(*buf_it).prevPhysReg);
740 // Decrement how many instructions are available.
741 --insts_available;
742 }
1275
743
1276 buf_it++;
1277 }
744 // Check if there's any instructions left that haven't yet been renamed.
745 // If so then block.
746 if (block_this_cycle) {
747 block();
748
749 toDecode->renameInfo.stall = true;
750 } else {
751 // If we had a successful rename and didn't have to exit early, then
752 // reset numInst so it will refer to the correct instruction on next
753 // run.
754 numInst = 0;
1278 }
1279}
755 }
756}